Semiconductor device and writing method

Details Semiconductor device and writing method Semiconductor device and writing method

2007-06-05

2007-06-05

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185030, C365S185220, C365S189050

Reexamination Certificate

active

11194023

ABSTRACT:
A semiconductor device has a memory cell array including a multi-level memory cell having multiple and different threshold values, a first latch circuit latching information of multiple-word of input information, a second latch circuit latching write information in which the information of the multiple-word of the input information is converted into information according to each level of the multi-level memory cell, a write circuit writing information into the multi-level memory cell on a group basis corresponding to the number of memory cells simultaneously programmable, according to the write information, and a control circuit controlling programming the memory cell array. The information is simultaneously programmed on the group basis into which multiple-word input information is divided, and makes it possible to shorten a program period substantially on a word basis. The program period is not increased, even if programming and verification are repeated several times in programming the multi-level memory cell.

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