Semiconductor device and wire bonding chip size package...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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C257S499000

Reexamination Certificate

active

11214983

ABSTRACT:
A semiconductor device incorporated in a wire bonding chip size package (WBCSP) is designed such that a plurality of pads are formed on the surface of a semiconductor substrate and are connected to external terminals via conductive posts, wherein first and second rewiring patterns are respectively connected to the pads. All elements are sealed within an insulating layer such that the external terminals are partially exposed on the surface, wherein an uppermost portion of a conductive wire is positioned above the rewiring patterns and is also positioned below the lower ends of the external terminals. This realizes short wiring distances between the pads and the external terminals; hence, it is possible to reduce the wiring resistance and wiring delay time; it is possible to increase a freedom of degree regarding wiring without causing short-circuit failure; and, it is possible to easily change the wiring in a short period of time.

REFERENCES:
patent: 6952048 (2005-10-01), Terui
patent: 6-302604 (1994-10-01), None
patent: H11-284020 (1999-10-01), None
patent: 2000-068405 (2000-03-01), None
patent: 2001-085609 (2001-03-01), None
patent: 2003-174118 (2003-06-01), None
patent: 2003-273154 (2003-09-01), None
patent: 2004-031562 (2004-01-01), None

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