Semiconductor device and the method for manufacturing the same

Details Semiconductor device and the method for manufacturing the same Semiconductor device and the method for manufacturing the same

2001-03-05

2004-07-20

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S688000, C257S778000, C257S774000

Reexamination Certificate

active

06765299

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and to the method for manufacturing the same. In particular, this invention relates to a chip size package, which has a plurality of semiconductor chips.
2. Description of the Related Art
Electronic appliances are becoming smaller and lighter as a result of developments in the semiconductor industry and customer' demands. One of the technologies for providing compact packages is called Chip Size Package (CSP). A CSP has approximately the same size as a semiconductor chip. And one of the technologies for providing integrated circuitry for use in such appliances is called Multi-Chip Packaging (MCP) or called Multi-Chip Module (MCM).
It is difficult for a CSP without an intermediate substrate, which is called an interposer, to include a plurality of chips. However, a CSP with an intermediate substrate is bigger and more expensive than the CSP without an interposer.
SUMMARY OF THE INVENTION
A semiconductor device includes a first semiconductor chip having a plurality of pads, a second semiconductor chip having a plurality of pads, the second semiconductor chip being fixed over a main surface of the first semiconductor chip, an insulating layer formed between the first semiconductor chip and the second semiconductor chip a plurality of conductive posts formed over the main surface of the first semiconductor chip and a main surface of the second semiconductor chip, the plurality of conductive posts being electrically connected to the plurality of pads on the first semiconductor chip and the plurality of pads on the second semiconductor chip and a resin covering the main surfaces of the first and second semiconductor chips, the resin partially covering the plurality of conductive posts.


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