Semiconductor device and testing method for semiconductor...

Details Semiconductor device and testing method for semiconductor... Semiconductor device and testing method for semiconductor...

2007-06-05

2007-06-05

Dinh, Son (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S201000, C365S203000, C365S194000

Reexamination Certificate

active

11262937

ABSTRACT:
To test a memory operation at as high speeds as high clock frequencies only with low clock frequencies. A semiconductor device according to an embodiment of the present invention includes: a clock output part; and a delay circuit, the clock output part setting a first state in accordance with an input of a first clock, setting a second state in accordance with an input of a delay clock from the delay circuit, and setting a third state in accordance with an input of a second clock, and the delay circuit delaying the first clock to output the delayed first clock as the delay clock. With this configuration, it is possible to test precharge and read/write access processings at as high operational speeds as high clock frequencies.

REFERENCES:
patent: 6104651 (2000-08-01), Cowles et al.
patent: 6269036 (2001-07-01), Shubat
patent: 6794678 (2004-09-01), Hasegawa et al.
patent: 6907555 (2005-06-01), Nomura et al.
patent: 7162671 (2007-01-01), Hasegawa et al.
patent: 2002-230999 (2002-08-01), None

Affiliated with

Also associated with

Rating

Semiconductor device and testing method for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and testing method for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and testing method for semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3821443