Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
2003-02-21
2004-10-19
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C257S288000, C257S355000, C257S356000, C257S358000, C257S365000, C257S175000, C361S056000, C361S091200, C361S111000, C361S058000
Reexamination Certificate
active
06806516
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a system. More particularly, the present invention relates to a technique usable effectively for an input circuit in each LSI/IC used in a system constituted of a plurality of LSIs/ICs, each having an input/output interface corresponding to a signal voltage different from others.
In an investigation of some well-known examples performed after the completion of the present invention, the present inventor et al have received a report of existence of official gazettes of (1) Japanese Unexamined Patent Publication No. Hei 5(1993)-266666 and (2) Japanese Unexamined Patent Publication No. 2001-251176 that are related to the present invention. The official gazette (1) discloses a semiconductor memory that can prevent transistors from destruction that might occur in the input circuit with use of an input amplitude limiting circuit disposed between an input terminal and the input circuit. The official gazette (2) discloses a level shifting circuit provided with a control circuit
30
for controlling a transfer gate
20
. The transfer gate
20
is controlled not so as to receive a voltage over a predetermined withstand voltage of the gate oxide film even when the input voltage exceeds the predetermined withstand voltage.
SUMMARY OF THE INVENTION
In recent years, high-end systems have come to use LSIs/ICs (hereinafter, to be just described as the LSIs) that employ the latest process technique at their core portions on which the system performance depends significantly while they use the LSIs that employ the previous or older process technique at their test/evaluation controlling portions that do not affect the system performance so much. Consequently, the latest LSIs come to be required to support both of the input/output interface related to the core portion and such the input/output interface related to the test/evaluation control portion. Generally, the signal voltage of the latter interface is higher than that of the former interface, so that each of the latest LSIs are also required to have an input circuit for converting a high signal voltage to a low one.
In the case of the official gazette (1), however, the input circuit used for signal voltage conversion as described above has many elements, so that the circuit power consumption increases. The input circuit is thus not considered to be practical so much. On the other hand, in the case of the official gazette (2), the input circuit clamps a signal level with use of a transfer gate MOSFET. For example, the input circuit of which supply voltage is 1.5V clamps an input voltage at 1.5V at the node A even when the input voltage of 1.5V or over is input to the input terminal. Thus, the input voltage never exceeds the 1.5V. When the withstand voltage of the input circuit MOS transistors is 1.8V and the input terminal IN comes to receive a voltage of 1.8V or over, therefore, the input circuit can avoid withstand voltage defects that might occur in the MOS transistors.
In spite of this, when the input voltage is excessively high, the voltage comes to cause a withstand voltage defect in the transfer gate MOSFET itself. This is because the upper limit of the input voltage becomes 3.3V (=1.5V+1.8V) if the supply voltage is 1.5V and the withstand voltage of the transfer gate MOSFET is 1.8V. Concretely, in the conventional example (2), the input voltage has an upper limit and if the input circuit receives a voltage over this upper limit, a withstand voltage defect occurs in a MOS transistor of the input circuit. One of the effective processes for preventing such the withstand voltage defect is to increase the thickness of the gate oxide film of the transfer gate MOSFET so as to increase the withstand voltage of the transistors.
FIG. 16
shows a cross sectional view of an element structure examined by the present inventor as described above. In
FIG. 16
, a MOSFET
9
is used as a transfer MOSFET and an MB
1
is shown as a MOSFET constituting the input circuit. In
FIG. 16
, reference symbols are defined as follows; SUB denotes a semiconductor substrate, W denotes a well, S denotes the source, D denotes the drain, and G denotes the gate of a MOS transistor. For example, the SUB, S, and D are N-type while the W is P-type. Both of the MOSFET
9
and the NB
1
are shown as N-channel MOS transistors. As shown in
FIG. 16
, the gate oxide film of the MOSFET
9
increases to that of the MOSFETMB
1
so as to increase the withstand voltage of the MOSFET
9
. If the gate oxide film thickness differs between the MOSFET
9
and the MB
1
in the same semiconductor device, the process will be complicated, thereby the manufacturing cost of the semiconductor device increases.
Under such circumstances, it is an object of the present invention to provide a semiconductor device improved to prevent withstand voltage defects that might occur in MOSFETs without having the process complicated. It is another object of the present invention to provide a system to be developed easily and prevented from withstand voltage defects that might occur in its semiconductor devices. The above and further objects and novel features of the present invention will appear more fully from the detailed description when the same is read in connection with the accompanying drawings.
In order to achieve an object, the semiconductor device of the present invention is constituted as follows. The voltage of each signal inputted from an external terminal is divided by first and second resistance means of the semiconductor device, then transmitted to an input circuit while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistance means. The input circuit forms an internal signal from the divided voltage received from the resistance means so as to reduce the signal amplitude, then transmits the signal to an internal circuit. Each of the input circuit and the internal circuit is constituted by MOSFETs manufactured in the same process.
Furthermore, in order to achieve another object, the system of the present invention comprises a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device includes first and second resistance means used to divide the voltage of a first signal inputted from a first external terminal and transmit the divided voltage to an input circuit and the AC component of the input signal to the input circuit through a capacitor disposed in parallel to the first resistance means. The first semiconductor device also includes a first input circuit that receives the divided voltage and a second input circuit that receives a second input signal from a second external terminal. The second input signal has a smaller amplitude than that of the first input signal. Each of the first and second input circuits is constituted by MOSFETs manufactured in the same process. The second semiconductor device forms an input signal corresponding to the first input circuit, then it is connected to the first semiconductor device. The third semiconductor device forms an input signal corresponding to the second input circuit, then it is connected to the first semiconductor device.
REFERENCES:
patent: 4394590 (1983-07-01), Honda
patent: 5463520 (1995-10-01), Nelson
patent: 5610426 (1997-03-01), Asai et al.
patent: 6013932 (2000-01-01), Chevallier
patent: 6492686 (2002-12-01), Pappert et al.
patent: 01248554 (1989-10-01), None
patent: 05-266666 (1992-03-01), None
patent: 06-061831 (1992-08-01), None
patent: 07-086904 (1993-09-01), None
patent: 07-321628 (1995-05-01), None
patent: 2001-251176 (2000-03-01), None
Kanetani Kazuo
Kazama Hideto
Nambu Hiroaki
Negishi Takemi
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Flynn Nathan J.
Forde Remmon R.
Reed Smith LLP
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