Semiconductor device and switching element

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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Details

C257S686000, C257S401000, C257S288000, C257S341000, C257S350000, C438S108000, C438S109000, C361S091200, C361S091100, C361S091500, C361S718000, C361S760000

Reexamination Certificate

active

07030501

ABSTRACT:
A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.

REFERENCES:
patent: 6055148 (2000-04-01), Grover
patent: 6184585 (2001-02-01), Martinez et al.
patent: 6282107 (2001-08-01), Vinciarelli
patent: 6307755 (2001-10-01), Williams et al.
patent: 6319755 (2001-11-01), Mauri
patent: 6566760 (2003-05-01), Kawamura et al.
patent: 6670217 (2003-12-01), Milla et al.
patent: 6734568 (2004-05-01), Matsuo et al.
patent: 6831351 (2004-12-01), Hirao et al.
patent: 10223835 (1998-08-01), None

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