Semiconductor device and SRAM having plural power supply voltage

Details Semiconductor device and SRAM having plural power supply voltage Semiconductor device and SRAM having plural power supply voltage

1997-07-10

1998-10-20

Nelms, David C.

Static information storage and retrieval

Powering

36518909, 257372, G11C 700

Patent

active

058257071

ABSTRACT:
A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well bias voltage (V.sub.BP1) is applied to the first well (N-type) and a second well bias voltage (V.sub.BN1) is applied to the second well (P-type); a second circuit (201; 202) formed in a third well (N-type) and a fourth well (P-type) of the same semiconductor substrate as above, supplied with the first supply voltage (V.sub.ss) and a third supply voltage (V.sub.cc2) higher than the first supply voltage but different from the second supply voltage (V.sub.cc), and activated when a third well bias voltage (V.sub.BP2) is applied to the third well (N-type) and a fourth well bias voltage (V.sub.BN2) is applied to the fourth well (P-type); a first bias circuit (20) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the first well bias voltage (V.sub.BP1); a second bias circuit (21) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the second well bias voltage (V.sub.BN1); a third bias circuit (16) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the third well bias voltage (V.sub.BP2); and a fourth bias circuit (17) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the fourth well bias voltage (V.sub.BN2). In the semiconductor device, even if any of the second supply voltage (V.sub.cc) and the third supply voltage (V.sub.cc2) is first supplied, it is possible to prevent the latch-up phenomenon caused by the floated substrate potential.

REFERENCES:
patent: 4862415 (1989-08-01), Nakano
patent: 5192883 (1993-03-01), Kimura
patent: 5305275 (1994-04-01), Yamashita et al.
patent: 5321647 (1994-06-01), Bronner et al.
patent: 5497023 (1996-03-01), Nakazato et al.

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