Semiconductor device and semiconductor module

Details Semiconductor device and semiconductor module Semiconductor device and semiconductor module

2001-03-29

2003-03-04

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Portion of housing of specific materials

C257S738000, C257S784000, C257S787000

Reexamination Certificate

active

06528879

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor module, and relates in particular to a technique for preventing a defect due to the mismatching of thermal expansion coefficients when a semiconductor device is mounted on a substrate.
2. Description of the Related Art
To produce a hybrid integrated circuit for installation in an electronic apparatus, a conductive pattern is formed on a printed circuit board, a ceramic substrate or a metal substrate, and an active element, such as an LSI or a discrete TR, and a passive element, such as a chip capacitor, a chip resistor or a coil, are mounted thereon. The conductive pattern and these elements are electrically connected to provide a circuit capable of performing a predetermined function.
FIG. 24
is a diagram of such a circuit, an audio circuit, the elements of which are mounted as shown in FIG.
25
.
In
FIG. 25
, straight, peripheral lines describe a rectangular substrate
1
having a surface that is, at the least, insulated. Adhered thereto is a conductive pattern
2
, composed of Cu. The conductive pattern
2
is composed of an external connecting electrode
2
A, a wire line
2
B, a die pad
2
C, a bonding pad
2
D, and an electrode
4
, fixed to the passive element
3
.
A bare chip, consisting of a TR, a diode, a composite element or an LSI, is soldered to the die pad
2
C, and the electrode on the chip and the bonding pad
2
D are electrically connected by fine metal lines
5
A,
5
B and
5
C, each of which is generally divided into a low signal portion and a high signal portion. An Au or Al line
5
A of about 40 &mgr;m &phgr; is employed for the low signal portion, and an Au or Al line of about 100 to 300 &mgr;m &phgr; is employed for the high signal portion. Especially, since the high signal portion has a large diameter, while taking manufacturing costs into account, an Al line
5
B of 150 &mgr;m &phgr; and an Al line
5
C of 300 &mgr;m &phgr; are employed.
A power TR
6
though which a large current flows is securely fixed to a heat sink
7
on a die pad
2
C in order to prevent a rise in the temperature of the chip.
The line
2
B is extended to various locations in order to form the circuit for the external drawing electrode
2
A, the die pad
2
C, the bonding pad
2
D and the electrode
4
. Further, when lines intersect each other because of their disposition on the chip and when they must be extended, jumper lines
8
A and
8
B are employed.
An example semiconductor device to be mounted in the substrate
1
is a semiconductor device packaged using an insulating resin. As such a packaged semiconductor device there is a lead frame type semiconductor device, wherein a semiconductor chip is mounted in a lead frame and the resultant structure is packaged using an insulating resin; a support substrate type semiconductor device, wherein a semiconductor chip is mounted on a ceramic support substrate, a printed circuit board or a flexible sheet, and the resultant structure is packaged using an insulating resin; or a plated type semiconductor device, wherein a semiconductor chip is mounted on a plated electrode and the resultant structure is packaged. It should be noted that the plated type semiconductor device is described in detail in JP-A-3-94431.
FIG. 26A
is a schematic diagram showing the plated type semiconductor device. Conductive paths
10
A to
10
D are formed of a plated film, a semiconductor chip
11
is securely bonded to the die pad
10
A, and the bonding pad on the semiconductor chip
11
and the plated bonding pad
10
B are electrically connected by a fine metal line
12
. A passive element
13
is bonded between the electrodes
10
C and
10
D via a brazing material. And since the plated film is embedded in the insulating resin without using a support substrate, a thin semiconductor device can be provided.
As is described above, a semiconductor device packaged using various methods is mounted on the substrate
1
. However, when a lead frame type semiconductor device is packaged, since lead projects outward from the package, the area of the substrate occupied by the device is expanded, and the size of the substrate must accordingly be increased. In addition, the lead frame could be cut or a burr could be left on the lead. Furthermore, for the support substrate type semiconductor device, since a support substrate is employed, the semiconductor device will be thicker, and accordingly, the weight of the device will be increased. Further, although a thin and compact plated type semiconductor device can be made because no support substrate is employed and because no lead projects outward from the package, the following problem has arisen.
For the explanation of the problem, in
FIG. 26B
an enlarged diagram is shown of a portion enclosed by a broken-line circle in FIG.
26
A. Included in this portion is a conductive path
10
B, which is formed by plating and is represented as a set of trigonal pyramids; solder
17
; a substrate
15
; and a conductive pattern
16
adhered to the substrate
15
.
The plated film is generally deposited by electrolytic plating, and has a crystal structure that assumes a tapered pillar shape. This structure is represented by using the trigonal pyramids. Since when formed the plated film is thin and has a polycrystalline structure, it is mechanically weak, and cracks tend to occur due to differences in the thermal expansion coefficient of the insulating resin. In addition, the grain boundary easily diffuses an externally supplied material. Thus as one problem, the flux used for soldering or an external ambient gas, such as moisture, may enter via the connection for the fine metal line
12
, and at the grain boundary, cause deterioration of the connection strength. Further, as another problem, when an electrode
10
B is formed using Cu plating, the solder layer underneath is diffused and eats into the plated film, thereby deteriorating the strength of the connection with the fine metal line.
In addition, when an elongated plated film is formed as a wire line, line disconnection may occur due to mismatching with the thermal expansion coefficient of the insulating resin. Similarly, when the plating type semiconductor device is mounted in the substrate, cracks also occur in wire lines due to mismatching with the thermal expansion coefficient of the substrate, and causes line disconnections or increases in line resistance. Especially when a long wire line is formed using the plated electrode
10
B, stress is generated in proportion to the length. Therefore, differences in the thermal expansion coefficient of the insulating resin
14
or the substrate
15
aggravates defects in the plated film and degrades reliability even more.
SUMMARY OF THE INVENTION
To resolve these shortcomings, according to a first aspect of the invention, a semiconductor device comprises:
a plurality of conductive paths formed of a conductive material whose crystal growth is large in the X and Y directions;
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin which is coated on the semiconductor chip and fills separation grooves between the conductive paths, thereby integrally supporting the conductive paths while the back surfaces of the conductive paths are exposed.
As is shown in
FIG. 1A
, a film that experiences more growth along the Z axis than along the X-Y axis is called a Z film, and a film that experiences more growth along the X-Y axis than along the Z axis is called an X-Y film. The Z film may be a plated film grown using an electrolytic process or an electroless process, and the X-Y film is a film, such as rolled copper foil, formed by rolling.
As is shown in the cross section of the X-Y film in
FIG. 1C
, since the individual crystals are laminated, spreading along the X-Y axis, the area size of the grain boundary is smaller than the Z film in FIG.
1
A. Therefore, the phenomenon of diffusion or transmission through the grain boundary is considerably restricted. The Z film in
FIG. 1B
is so

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