Semiconductor device and semiconductor memory device

Details Semiconductor device and semiconductor memory device Semiconductor device and semiconductor memory device

2005-07-19

2005-07-19

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S210130

Reexamination Certificate

active

06920079

ABSTRACT:
A semiconductor memory device according to the present invention includes: a plurality of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells arranged in an array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and a plurality of dummy transistors32-jeach of which is formed between two adjacent ones of the plurality of N-ch MOS transistors30-kso as to share diffusion layers with adjacent N-ch MOS transistors30and each of which has a gate electrode supplied with a voltage for electrically insulating these adjacent transistors30-k.

REFERENCES:
patent: 6088286 (2000-07-01), Yamauchi et al.
patent: 6242782 (2001-06-01), Casper et al.
patent: 6646300 (2003-11-01), Ishii et al.
patent: 2001-344989 (2001-12-01), None

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