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Reexamination Certificate

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C365S229000, C365S189090

Reexamination Certificate

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06940777

ABSTRACT:
An operating current is supplied from a power supply node to an internal circuit. In a test mode, current supply from a power supply to the power supply node is stopped by a current switch, and an externally adjustable test current is supplied to the power supply node. The test current is set in accordance with an acceptable value of a leakage current in the internal circuit. Evaluation is made as to whether the leakage current in the internal circuit is not greater than the acceptable value, in accordance with an output of a voltage comparison circuit detecting a voltage drop at the power supply node.

REFERENCES:
patent: 5644250 (1997-07-01), Ooishi
patent: 5920226 (1999-07-01), Mimura
patent: 6184744 (2001-02-01), Morishita
patent: 6201754 (2001-03-01), Ooishi et al.
patent: 6256224 (2001-07-01), Perner et al.
patent: 6329873 (2001-12-01), Morishita
patent: 6337828 (2002-01-01), Ooishi et al.
patent: 6347056 (2002-02-01), Ledford et al.
patent: 2003/0081453 (2003-05-01), Hidaka
patent: 11-339470 (1999-12-01), None
Roy Scheuerlein et al., “A 10ns Read and Write Non-Volatile Memory Array using a Magnetic Tunnel Junction and FET Switch in Each Cell,” IEEE ISSCC Digest of Technical Papers, Feb. 2000, pp. 94-95, 128-129, 409-410.
NIKKEI Microdevices, “Forefront of Non-Volatile Memory The Future in Intel's Mind: From Flash Memory to “OUM”,” Mar. 2002, pp. 65-78 (with partial English Translation).

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