Semiconductor device and semiconductor integrated circuit...

Details Semiconductor device and semiconductor integrated circuit... Semiconductor device and semiconductor integrated circuit...

1999-09-23

2002-05-28

Chaudhuri, Olik (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S315000, C257S316000

Reexamination Certificate

active

06396086

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device which comprises a conductive film formed extending over an element isolation region and an element region
11
and has in the element region
11
a capacitor structure comprised of a semiconductor substrate, an insulating layer, and the conductive layer and, more particularly, to a semiconductor device used for MOSFET or MOS capacitor.
FIG. 31
shows an example of the shape of a conventional MOS capacitor.
FIG. 32
is a sectional view taken along the line XXXII—XXXII in FIG.
31
.
On a silicon substrate
10
, an element isolating insulation film
12
having an STI (Shallow Trench Isolation) structure is formed. The element isolating insulation film
12
constitutes an element isolation region, defining an element region
11
in the silicon substrate
10
. The element region
11
has a square shape which has four sides and four corners.
In the substrate
10
within the element region
11
, there is formed a diffusion layer
13
which has the same conductivity type as that of the silicon substrate
10
and has an impurity concentration higher than that of the silicon substrate
10
. Connected to the diffusion layer,
13
is a wiring
14
which is provided for setting a potential of the silicon substrate
10
.
A silicon oxide film
15
is formed on the substrate
10
within the element region
11
. Further, a conductive film
16
is formed on the element isolating insulation film
12
and on the silicon oxide film
15
. The conductive film
16
is composed of a metal, a semi-conductor containing an impurity, or the like. The conductive film
16
is formed extending over the element separation region and the element region
11
, and, in the element region
11
, a capacitor structure is formed which is comprised of the silicon substrate
10
, the silicon oxide film
15
and the conductive film
16
. Further, the conductive film
16
covers three sides S
1
, S
2
, and S
3
and two corners C
1
and C
2
of the element region
11
.
An interlayer insulation film (such as a TEOS film or a BPSG film)
17
is formed on the conductive film
16
. The wiring
14
and a wiring
18
are formed on the interlayer insulation film
17
. The wiring
14
is connected to the diffusion layer
13
via a contact hole
19
, and the wiring
18
is connected to the conductive film
16
via a contact hole
20
.
In the MOS capacitor having the above-mentioned structure, the conductive film
16
covers three sides S
1
, S
2
, and S
3
and two corners C
1
and C
2
of the element region
11
. This is for assuring the maximum capacitor area even if a misalignment takes place when the patterning of the conductive film
16
is made.
However, such a structure has a disadvantage that, in case that a voltage is applied across the silicon substrate
10
and the conductive film
16
, the electric field concentrates in the sides S
1
, S
2
, and S
3
and corners C
1
and C
2
of the element region
11
covered by the conductive layer
16
, when viewed in the plan view of
FIG. 31
, that is, in an end portion D of the element region
11
covered by the conductive film
16
, when viewed in the sectional view of FIG.
32
. In particular, in the corners C
1
and C
2
of the element region
11
, this electric field concentration is noticeably caused.
The reason why electric field concentration noticeably occurs in the corners C
1
and C
2
of the element region
11
is that, at the corners C
1
and C
2
of the element region
11
, the edges of the element region
11
are tapered when seen both in the plan view and in the sectional view, and these corners C
1
and C
2
are covered by the conductive film
16
. This point will be described later in more detail in connection with the manufacturing method of the semiconductor device.
Further, if the electric field concentrates in the capacitor insulation film (silicon oxide film
15
) of the MOS capacitor, at the corners C
1
and C
2
of the elements region
11
, then breakdown becomes apt to occur in the capacitor insulation film, at the corners C
1
and lowering the reliability and the manufacturing yield of semiconductor devices.
The method of manufacturing the MOS capacitor shown in FIG.
31
and
FIG. 32
will be described below.
First, as shown in
FIG. 33
, a buffer silicon oxide film
21
is formed by thermal oxidation on the silicon substrate
10
. Further, by the LPCVD method, a silicon nitride film
22
which functions as a mask material when CMP (chemical mechanical polishing) is performed is formed on the buffer silicon oxide film
21
.
Next, as shown in
FIG. 34
, on the silicon nitride film
22
, a resist pattern for defining the element isolation region and the element region
11
from each other is formed by a photolithography step, and, by performing anisotropic etch (such as RIE) using this resist pattern as a mask, the silicon nitride film
22
, the buffer silicon oxide film
21
and the silicon substrate
10
are successively etched. As a result, in the substrate
10
, there is formed a trench
23
which constitutes the element isolation region. After this, the resist pattern is removed.
Next, as shown in FIG.
35
and
FIG. 36
, a silicon oxide film is formed by the LPCVD method over the surface of the silicon substrate
10
so as to sufficiently fill up the trench
23
. After this, by CMP, this silicon oxide film is polished under the condition that the silicon nitride film
22
is made to serve as a stopper. As a result, the silicon oxide film is left only in the trench
23
, and thus, the element isolating insulation film
12
of STI structure is formed.
Next, as shown in FIG.
37
and
FIG. 38
, the silicon nitride film
22
which is a mask material is removed by hot phosphoric acid treatment. Further, by dilute hydrofluoric acid treatment, the buffer silicon oxide film
21
is removed.
Here, when the buffer silicon oxide film
21
is removed, the surface portion of the element isolating insulation film
12
comprised of a silicon oxide film is also etched. The element isolating insulation film
12
, which is sufficiently thick as compared with the buffer silicon oxide film
21
, is not all removed, however, particularly, the corner portions of the element region
11
are noticeably etched when seen in a plan view, or the element isolating insulation film
12
is noticeably etched in the end portion D of the element region
11
when seen in a sectional view, and thus, these portions are exposed.
The cause for the occurrence of such a phenomenon is considered to lie in the film quality (density) of the element isolating insulation film
12
. That is, when the silicon oxide film is buried into the trench
23
, the density of the silicon oxide film in the corner portions of the element region
11
become lower than that of the other portion in some cases, depending on the depositing condition of the CVD. In general, the etching rate of a silicon oxide film is larger in the low density portion than in the high density portion thereof, so that, particularly, the silicon oxide film in the corners of the element region
11
is noticeably etched, and thus, the corners of the element region
11
become apt to be exposed.
Next, as shown in FIG.
39
and
FIG. 40
, the silicon oxide film
15
is formed by thermal oxidation on the silicon substrate
10
in the element region
11
.
Further, as shown in FIG.
41
and
FIG. 42
, a conductive film (such as a polycrystalline silicon film)
16
is formed by the LPCVD method on the element isolating insulation film
12
and on the silicon oxide film
15
. A resist pattern is formed by photolithography, and, using this resist pattern as a mask, the conductive film
16
is patterned by anisotropic etching. After this, the resist pattern is removed off.
Here, the conductive film
16
covers the corners of the element region
11
through the silicon oxide film
15
. Due to this, in case a voltage is applied between the silicon substrate
10
and the conductive film
16
, the electric field concentrates in the portions of the silicon oxide fil

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