Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Housing or package filled with solid or liquid electrically...
Reexamination Certificate
2002-04-25
2004-09-07
Nguyen, Van Thu (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Housing or package filled with solid or liquid electrically...
C257S688000, C257S689000, C257S690000, C257S693000
Reexamination Certificate
active
06787892
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a chip size package (CSP) and a manufacturing method thereof, and more specifically, it relates to a technology characterized by the structure of information (hereafter referred to as index marks) such as characters or symbols that indicate the direction along which the package is mounted at a mounting substrate and the direction of the package itself.
DESCRIPTION OF THE RELATED ART
The chip size package (CSP) technology in which the size of a semiconductor device package is set roughly equal to or slightly larger than the size of the semiconductor chip (bare chip) is adopted to realize high-density mounting of semiconductor devices on a mounting substrate. By setting connection terminals (external connection terminals) used to achieve connections with the mounting substrate in a grid pattern at the main surface (circuit forming surface) of a semiconductor chip formed in a roughly square shape, the size of the semiconductor device package can be set substantially equal to or slightly larger than the size of the semiconductor chip. Such a chip size package requires a smaller area to be occupied by the semiconductor device mounted on the mounting substrate and, at the same time, since it reduces the length of wiring used to connect the electrodes on the semiconductor chip and the external connection terminals, it achieves an improvement in the operating speed of the semiconductor device.
There is also a technology proposed in the related art that is achieved by packaging a semiconductor device still in a wafer state (hereafter referred to as a wafer-level CSP). A wafer-level CSP is packaged before cutting out individual semiconductor chips from the wafer. The wafer-level CSP technology, which allows an integration of the packaging process and the wafer process, achieves an advantage in that the production cost can be greatly reduced.
An index mark is provided at a semiconductor device. This index mark is added to indicate the direction along which the semiconductor device is mounted at the mounting substrate. In the semiconductor device in a wafer-level CSP, for instance, the index mark is normally provided on the rear surface (a circuit non-forming surface) of the semiconductor device so as to allow the semiconductor substrate mounting direction to be visually ascertained when mounting the semiconductor device at the mounting substrate.
However, since index marks must be added at individual semiconductor devices in the index mark indication system adopted in the related art, the following problems arise.
1) It is necessary to adjust the positional relationship of an index mark to the corresponding semiconductor device on a one-on-one the basis. This sets a limit to the processing capability and also requires a special process for adding the index marks.
2) Ink-based index marks, for instance, may become worn off to disable the directional verification, whereas index marks formed by using laser light or the like may cause a degradation in the internal circuit pattern attributable to the laser light transmitted through the silicon layer.
3) The adjustment of the positional relationship of the index mark and the semiconductor device becomes more difficult as the size of semiconductor device is reduced. In addition, as the index mark itself becomes smaller in a smaller semiconductor device, the verification of the mounting direction that must be performed when mounting the semiconductor device at the mounting substrate also becomes more difficult.
SUMMARY OF THE INVENTION
An object of the present invention, which has been completed by addressing the problems of the semiconductor devices in the prior art discussed above, is to provide a new and improved semiconductor device and a new and improved semiconductor device manufacturing method that allow an index mark to be provided through a simpler process.
Another object of the present invention is to provide a new and improved semiconductor device and a new and improved semiconductor device manufacturing method that prevent an index mark from coming off and also prevent degradation of the circuit pattern.
Yet another object of the present invention is to provide a new and improved semiconductor device and a new and improved semiconductor device manufacturing method that allow easy adjustment of the position of an index mark relative to the external dimensions of the semiconductor device and facilitate the verification of the mounting direction when the semiconductor device is mounted at a mounting substrate even when the size of the semiconductor device is reduced.
In order to achieve the objects described above, in a first aspect of the present invention, a semiconductor device comprising a semiconductor substrate that includes a main surface having a circuit element formed thereupon, a plurality of electrode pads formed at an upper portion of the main surface of the semiconductor substrate and electrically connected with the circuit element, a sealing resin that seals the upper portion of the main surface of the semiconductor substrate and a plurality of external connection terminals formed at the upper portion of the main surface of the semiconductor substrate so as to project out of the surface of the sealing resin and arranged in a substantially regular array over specific intervals from one another, characterized in that at least one of the plurality of external connection terminals is formed in a shape different from the shape of the other external connection terminals, is provided.
In order to achieve the objects described above, in another aspect of the present invention, a semiconductor device comprising a semiconductor substrate that includes a main surface having a circuit element with a specific function formed thereupon, a plurality of electrode pads formed at an upper portion of the main surface of the semiconductor substrate and electrically connected with the circuit element, a sealing resin that seals the upper portion of the main surface of the semiconductor substrate and a plurality of external connection terminals formed at the upper portion of the main surface so as to project out of the surface of the sealing resin and arranged in a substantially regular array over specific intervals from one another, which is characterized in that at least one of the side surfaces of the semiconductor device is colored differently from the other side surfaces, is provided.
In yet another aspect of the present invention, a semiconductor device comprising a semiconductor substrate that includes a first main surface having a circuit element formed thereupon and a second main surface facing substantially opposite the first main surface, a plurality of external terminals formed at an upper portion of the first main surface and electrically connected with the circuit element and a direction index mark constituted of a line segment which includes a start point and an end point and an end point mark added at the end point and is formed on the second main surface is provided.
In yet another aspect of the present invention, a semiconductor device manufacturing method achieved by first sealing semiconductor devices in a wafer state and then cutting out the individual semiconductor devices from the wafer, which is characterized in that information indicating the direction of the semiconductor devices is added onto a rear surface of the wafer before cutting out the individual semiconductor devices from the wafer, is provided.
REFERENCES:
patent: 6525422 (2003-02-01), Ono et al.
patent: 09-320911 (1997-12-01), None
patent: 10-308410 (1998-11-01), None
patent: 11-274361 (1999-10-01), None
Arai Kentarou
Furuya Yuuki
Iguchi Akihisa
Menz Doug
Nguyen Van Thu
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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