Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2011-08-30
2011-08-30
Andujar, Leonardo (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S758000, C257S798000, C257S776000
Reexamination Certificate
active
08008779
ABSTRACT:
Disclosed is a semiconductor device that includes: a semiconductor substrate; a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less; a conductor which covers a side face of the first insulating film at least near four corners of the semiconductor substrate, and at least an outer side face of which has a conductive barrier layer; and a second insulating film covering the outer side face of the conductor and having a relative dielectric constant of over 3.8. Also disclosed is a semiconductor device that includes: a conductor covering a side face of the first insulating film at least near four corners of the semiconductor substrate; and a corrosion resistant conductor formed at least near the four corners of the semiconductor substrate to extend from directly under the second insulating film to directly under the conductor.
REFERENCES:
patent: 5994762 (1999-11-01), Suwanai et al.
patent: 6207585 (2001-03-01), Hasegawa et al.
patent: 6313037 (2001-11-01), Kajita et al.
patent: 6498089 (2002-12-01), Komada
patent: 6770977 (2004-08-01), Kishida et al.
patent: 5-152433 (1993-06-01), None
patent: 06-097165 (1994-04-01), None
patent: 06-188240 (1994-07-01), None
patent: 10-189497 (1998-07-01), None
patent: 10-189733 (1998-07-01), None
patent: 10-209148 (1998-08-01), None
patent: 11-054504 (1999-02-01), None
patent: 2000-277465 (2000-10-01), None
patent: 2001-196415 (2001-07-01), None
patent: 2002-270608 (2002-09-01), None
patent: 2002-353307 (2002-10-01), None
Wolf et al., Silicon Processing for the VLSI Era, 2000, vol. I, Lattice Press, 719-727, 791-795.
Notification of the First Office Action from the Patent Office of the People's Republic of China, mailed Dec. 9, 2005.
Office Action from the Japanese Patent Office, mailed Oct. 24, 2006.
Notification of Reasons for Rejection from the Japanese Patent Office, dated Mar. 10, 2009 (3 pages).
Andujar Leonardo
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Semiconductor device and semiconductor device manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and semiconductor device manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and semiconductor device manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2669667