Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-10-23
2003-04-15
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S666000
Reexamination Certificate
active
06548891
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a production process thereof. More particularly, the present invention relates to a technology for simplifying the production process and reduce production costs, while considering prevention of adverse environmental effects in the production of semiconductor devices in which a semiconductor chip such as a bare chip and the like is attached onto a wiring substrate.
2. Description of the Related Art
In the production of semiconductor devices, to ensure electrical functions of a semiconductor element such as an IC chip or an LSI chip (hereinafter referred to as a “semiconductor chip”) after its formation and dicing on a silicon wafer, it is necessary to electrically connect an electrode of the semiconductor chip to a wiring pattern formed on the wiring substrate. Further, as is well-known in the art, a wire bonding system and a flip chip bonding system have been suggested for carrying out such electrical connection (the so-called attachment of chips).
In the wire bonding system, after formation of a wiring pattern on a wiring substrate, a semiconductor chip is bonded to a wiring substrate by adhering a lower surface (surface opposed to a surface having an electrode) of the semiconductor chip through an adhesive to a surface (wiring-bearing surface) of the wiring substrate, followed by electrically connecting through a bonding wire the electrode of the semiconductor chip with the wiring of the wiring substrate.
On the other hand, in the flip chip bonding system, after formation of the wiring pattern on the wiring substrate as in the wire bonding system mentioned above, a metal bump such as a solder bump is applied to an electrode pad of the semiconductor chip, and the metal bump is electrically connected through an anisotropic conductive sheet or the like to the wiring (land) on the wiring substrate.
More specifically, in all of the prior art electrical connection systems, it was necessary to separately conduct the formation of the wiring and attachment of chips. Further, in the attachment of chips, it was necessary to use a bonding means such as solder and the like for the electrical connection between the chip and the wiring.
SUMMARY OF THE INVENTION
As described above, according to the prior art methods, since the fabrication step for forming a wiring on a wiring substrate and the chip attachment step for electrically connecting the wiring with a semiconductor chip have to be separately carried out in the production of semiconductor devices, there was a problem in that the production process for the semiconductor devices was relatively complicated and thus the production cost increased.
Further, in the case wherein the semiconductor devices are produced by using a wire bonding connecting system, since a bonding wire is applied at a higher position than the surface level of the electrode on the semiconductor chip, there was a disadvantage in that the total height of the semiconductor devices is relatively increased. Such an increase in the height of the devices goes against a recent trend of producing thin semiconductor devices.
Further, there was a similar disadvantage in the production of semiconductor devices in using a flip chip bonding system, in that the total height of the semiconductor devices is relatively increased, because a bump has to be applied between a wiring substrate and a semiconductor chip. This is because the total height of the semiconductor devices increases relatively in conformity with the size of the applied bump.
Furthermore, since a soldering process is frequently used for the bonding of a wiring circuit with a semiconductor chip in the attachment of the chip, there was a problem in that a solder used may cause environmental pollution.
The present invention is therefore directed to solve the prior art problems, described above, in the production of semiconductor devices.
The object of the present invention is to provide a semiconductor device which enables production of the device in a simplified process and at a reduced production cost, and also enables a reduction in the thickness of the device while inhibiting adverse effects on the environment, along with a production process for such a semiconductor device.
In one aspect thereof, the present invention resides in a semiconductor device comprising a wiring substrate having attached thereon at least one semiconductor element, in which the semiconductor element is directly bonded through a Coulomb's force created between radicals of the atoms constituting the semiconductor element and reactive radicals on a surface of the wiring substrate, and a wiring pattern formed on the surface of the wiring substrate extends onto a surface of the semiconductor element and is electrically connecting with an electrode and the like formed on the surface of the semiconductor element.
In the semiconductor device according to the present invention, the semiconductor element used herein is not restricted to a specific one. As described above, the semiconductor element includes an IC chip, an LSI chip and others. Of course, if desired, the semiconductor device may include any other elements or parts which are conventional in the field of semiconductor devices. In the semiconductor device of the present invention, it is preferred that the wiring pattern, when viewed at an end portion of the semiconductor element, have a planarized surface. In other words, the height of the wiring pattern at such an end portion should be substantially the same as that of the wiring pattern on the wiring substrate, and the wiring pattern extends on a substantially even surface, i.e. there is no substantial step in a surface of the wiring pattern at the end portion of the semiconductor element adjacent to a portion having no underlying semiconductor element. Since the wiring pattern can be produced to have a substantially flat surface and a reduced thickness, it becomes possible to produce thinner semiconductor devices along with prevention of permeation of a liquid into a gap between the wiring pattern and the underlying semiconductor element or wiring substrate.
Further, the semiconductor element may be used without applying any surface treatment to a bonding surface thereof, but it is preferred that the bonding surface of the semiconductor element be subjected to a mirror polishing process to make a mirror surface. Since a Coulomb's force can be increased in proportion to the surface area of the bonding or contacting surface of the semiconductor element, increased bonding strength of the element can be obtained when the contacting surface is increased as a result of the polishing process.
A surface of the wiring substrate to which a semiconductor element is bonded is preferably activated with a plasma treatment to generate reactive radicals on the surface thereof. In this plasma treatment, if the wiring substrate used is made of a silicon substrate, it is preferred that the plasma treatment be carried out with irradiation of ultraviolet radiation.
Further, to ensure good electrical communication between an upper surface and a lower surface of the wiring substrate, it is preferred that the wiring substrate further have a conductor formed through the substrate. In the conductor formed through the wiring substrate, it is preferred that an end surface of the conductor exposed at a semiconductor element side of the wiring substrate be electrically connected with a wiring pattern formed on the wiring substrate. On the other hand, it is preferred that another end surface of the conductor exposed at another surface of the wiring substrate opposed to the semiconductor element side further comprise an external connecting terminal, although the other end surface of the conductor may be directly used as an external connecting terminal without applying any conducting means.
Furthermore, it is preferred that the wiring substrate and thus the semiconductor device have a protective insulating layer as the uppermost layer. The pre
Cao Phat X.
Paul & Paul
Shinko Electric Industries Co. Ltd.
LandOfFree
Semiconductor device and production process thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and production process thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and production process thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3084313