Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-08-23
2002-11-19
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S295000, C257S783000, C257S300000, C257S301000, C257S700000
Reexamination Certificate
active
06483167
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of production thereof; and, more particularly, the invention relates to a semiconductor device having a built-in dielectric device and the method of production thereof.
Since the DRAM (Dynamic Random Access Memory) has a large capacity, attempts are being made to produce its capacitor portion as a microstructure. To produce the capacitor as a microstructure, it is necessary to reduce the dielectric material thickness, to select materials having a high dielectric constant, and to design a three-dimensional structure comprising top/bottom electrodes and dielectrics. The publication Integration Processes of (Ba, Sr)TiO
3
capacitor for 1 Gb and Beyond [Byoung Teak Lee et al.; IEEE TECH. Dig., 1998, pp 815-818] describes a capacitor with 3-dimensional structure where a 5 nm conductive TiSiN film is formed as a glue layer between the Pt bottom electrode and the SiO
2
substrate. The aspect ratio (depth/width) of the 3-dimensional structure of this capacitor is about 3, and (Ba, Sr) TiO
3
(BST) is used to produce the dielectric. The BST dielectric film is prepared on the bottom electrode by the CVD (chemical vapor deposition) method.
Japanese Patent Laid-Open No. 243179/1999 discloses a capacitor portion having a flat dielectric and top/bottom electrodes of planer structure where the oxide layer comprising oxide IrO
2
or RuO
2
, and metallic layer comprising Ir or Ru are formed on the SiO
2
insulator films.
However, if separation occurs to the bottom electrode on the side wall of the holes in a 3-dimensional structure, a greater stress is caused by film separation since the aspect ratio is greater. This causes separation to more likely occur on the bottom electrode at the bottom, making it difficult to create a 3-dimensional structure.
The publication Integration Processes of (Ba, Sr)TiO
3
capacitor for 1 Gb and Beyond [Byoung Teak Lee et al.; IEEE TECH. Dig., 1998, pp 815-818] describes a capacitor where a TiN barrier, a TiSiN glue layer, a Pt bottom electrode and a BST dielectric are sequentially laid out on an Si plug. The Si in the TiSiN glue layer is likely to be oxidized in the process of heat treatment in an oxygen atmosphere, which is carried out after BST film formation, and part of the glue layer becomes a SiO
2
insulation film, resulting in poor conduction between the Si plug and Pt bottom electrode in some cases. Furthermore, the TiSiN glue layer and the Pt bottom electrode are produced by the sputtering method. In the case of a 3-dimensional structure having an aspect ratio of more then 3, this results in a poor coverage over level differences, and the deposition on the side wall of the holes is reduced below that on the surface and bottom, thereby presenting a problem in that a 3-dimensional structure cannot be created.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a method of production thereof, where means are provided to prevent film separation of the bottom electrode during the heat treatment process carried out to make the bottom electrode closed packed and in the heat treatment process for producing dielectric crystallization.
Another object of the present invention is to provide a highly integrated semiconductor and a method of production thereof, where said semiconductor has a 3-dimensional structure with an aspect ratio greater than 3.
The present invention achieves the foregoing objects by a technique which is characterized by a glue layer containing an insulator provided between the bottom electrode and the inner wall of the convex holes of the insulation layer.
The film of the bottom electrode produced by the CVD method includes residual elements of carbon, hydrogen and oxygen resulting from CVD material. In the heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization in an oxygen atmosphere, these residual elements are separated from the film of the bottom electrode, and the oxygen of the residual elements reacts with the metallic element of the bottom electrode, resulting in recrystallization of the bottom electrode and film shrinkage. However, the bonded film allows the bottom electrode film to be heavily bonded to the substrate SiO
2
, thereby preventing separation of the bottom electrode film from substrate SiO
2
.
In a device having 3-dimensional structure, the stress causing separation between the bottom electrode film and the substrate SiO
2
, is produced by shrinkage of bottom electrode film on the side wall of the holes. Especially, in a device having a 3-dimensional structure, where the aspect ratio is 3 or more, a greater force is produced by the bottom electrode film on the side wall of the holes to separate the bottom electrode film at the bottom of the holes from the barrier layer. By the present invention, however, the glue layer on the side wall of the holes alleviates the stress between the bottom electrode film on the side wall of the holes and the substrate SiO
2
. Even in a device having a 3-dimensional structure with an aspect ratio greater than 3, an effective conduction between the bottom electrode and Si plug is ensured by the present invention, without bottom electrode film on the bottom of the holes being separated from the barrier layer.
The present invention is further characterized by having three processes: a process of forming a glue layer on the inner wall of the holes formed on the insulating film by the CVD (chemical vapor deposition) method, a process of removing the glue layer from the barrier, and a process of forming a bottom electrode on the glue layer.
Use of the CVD (chemical vapor deposition) method allows a homogeneous glue layer to be formed even in a device having a 3-dimensional structure with an aspect ratio greater than 3.
A metallic film containing at least any one of Ti, Ta, W and Cu provided on the inner wall of the holes, formed on the insulating film, such as SiO
2
, allows this metallic film and the substrate SiO
2
to be bonded closely to each other, since Ti, Ta, W and Cu is extremely adhesive with SiO
2
. Furthermore, this metallic film is oxidized in the bottom electrode forming process, in the heat treatment process which is carried out to make the bottom electrode more closely packed, and in the heat treatment process for producing dielectric film crystallization in an oxygen atmosphere. Therefore, the glue layer containing at least one of Ti, Ta, W and Cu exhibits an excellent adhesion to both the substrate film and the bottom electrode. Even when exposed to impact or external damage in the processing after formation of the bottom electrode on the glue layer, separation on these interfaces is prevented by excellent adhesion of the glue layer with the insulating film and bottom electrode.
The glue layer, comprising a metallic oxide film, is formed by oxidizing the metallic film containing at least one of Ti, Ta, W and Cu. Not only that, a metallic film can be created using the metal containing at least one of Ti, Ta, W and Cu and another metal which does not easily oxidize, and a bonded film resulting from a mixture of metallic oxide and metal can be formed by oxidizing this film. Through formation of a metallic oxide in the glue layer, both types of bonded film alleviate the stress between the Ru film and the substrate SiO
2
resulting from recrystallization of the Ru film and film shrinkage.
This glue layer is first formed by metal. Metallic film has a large degree of freedom in etching conditions, and substantially reduces the etching speed of an insulating film, such as SiO
2
and barrier layer, permitting selective etching of the metallic film. Therefore, the glue layer can be formed only on the inner wall of the holes by etching prior to the glue layer being oxidized. If the film formed of a compound comprising ARuO
3
(A=Ba, Sr) or amorphous film including the constitute elements is used in the glue layer,
Fujiwara Tetsuo
Hayashibara Mitsuo
Kadoshima Masaru
Murata Yasuhiko
Nabatame Toshihide
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Le Thao P
Nelms David
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