Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
2001-07-05
2004-06-01
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S347000, C257S348000, C257S349000, C257S350000, C257S566000, C257S567000
Reexamination Certificate
active
06744115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a process of production of the same, more particularly a semiconductor device which prevents autodoping of an impurity from an insulating film to a conductive layer, especially to a polysilicon layer, to suppress fluctuations in characteristics and a process of production of the same.
2. Description of the Related Art
Various bipolar transistors, capacitors, or resistors are structured with a conductive layer comprised of for example polysilicon formed on a semiconductor substrate and with interconnections formed on them via an insulating film.
FIGS. 1
to
4
show examples of cross-sectional structures of these elements. Each element shown in
FIGS. 1
to
4
is formed on a p-type semiconductor substrate
1
and an n-type epitaxial layer
2
formed on the substrate
1
. In all the elements of
FIGS. 1
to
4
, a LOCOS
3
for separating elements is formed on the surface of the n-type epitaxial layer
2
. Below the LOCOS
3
is formed an element separating diffusion layer
4
. The element separating diffusion layer
4
reaches the p-type semiconductor substrate.
FIG. 1
shows a vertical npn transistor (below, referred to as an “V-npn”), while
FIG. 2A
shows a lateral pnp transistor (below, referred to as an “L-pnp”).
FIG.
2
B and
FIG. 3A
both show vertical pnp transistors.
FIG. 2B
shows a vertical pnp transistor comprising an n-type buried layer which separates electrically a p-type collector layer and the p-type semiconductor substrate. This is referred to as a “V-pnp” below. On the other hand,
FIG. 3A
shows a vertical pnp transistor wherein a p-type collector layer is formed to reach a p-type semiconductor substrate (substrate pnp). This is referred to as an “S-pnp” below.
FIG. 3B
shows a capacitor of a metal-insulator-semiconductor (MIS) structure (below, referred to as an “MIS-C”), while
FIG. 4
shows a polysilicon resistor (below, referred to as a “Poly-R”).
Below, the structure of each element mentioned above will be explained.
The V-npn of
FIG. 1
has an n-type collector buried layer
5
at the surface layer of the p-type semiconductor substrate
1
. The n-type epitaxial layer
2
above it is made an n-type collector layer. At the surface layer of the n-type epitaxial layer
2
comprised of the n-type collector layer is formed a p-type base region
6
. Around the p-type base region
6
is formed a graft base
6
a
. At the surface layer of the p-type base region
6
is formed an n-type emitter region
7
. Also, at the n-type epitaxial layer
2
is formed a collector plug region (n
+
sinker)
8
which connects to the n-type collector buried layer
5
.
On the n-type epitaxial layer
2
or the LOCOS
3
is formed for example a silicon oxide film
9
as a first insulating film. The silicon oxide film
9
on the p-type base region
6
is provided with an opening. In the opening and on the silicon oxide film
9
around the opening is formed a first polysilicon layer (p-type base electrode
10
) which is connected to the p-type base region
6
and serves as a base take-out part. The p-type base electrode
10
on the n-type emitter region
7
is provided with an opening.
On the p-type base electrode
10
or the silicon oxide film
9
is formed for example a silicon oxide film
11
as a second insulating film. The silicon oxide film
11
on the n-type emitter region
7
is provided with an opening. In the opening and on the silicon oxide film
11
around the opening is formed an n-type emitter polysilicon layer
12
. The n-type emitter polysilicon layer
12
connects to the n-type emitter region
7
and serves as an emitter take-out part.
On a part of the p-type base electrode
10
, on the n-type emitter polysilicon
12
and on the collector plug region
8
are formed electrodes
13
.
Next, as shown in
FIG. 2A
, the L-pnp has an n-type base buried layer
14
at the surface layer of the p-type semiconductor substrate. The n-type epitaxial layer
2
on the n-type base buried layer
14
becomes an n-type base layer. At the surface layer of the n-type epitaxial layer comprised of the n-type base layer are formed a p-type emitter region
15
and a p-type collector region
16
separate from each other. Also, in the n-type epitaxial layer
2
is formed a base plug region (n
+
sinker)
17
connected to the n-type base buried layer
14
.
On the n-type epitaxial layer
2
or the LOCOS
3
is formed for example a silicon oxide film
9
as a first insulating film. The silicon oxide film
9
on the p-type emitter region
15
and the p-type collector region
16
are provided with openings. At the opening on the p-type emitter region
15
is formed an emitter take-out electrode
18
comprised of a p-type polysilicon layer. In the same way, at the opening on the p-type collector region
16
is formed a collector take-out electrode
19
comprised of a p-type polysilicon layer.
Electrodes
13
are formed on each of the emitter take-out electrode
18
, collector take-out electrode
19
, and base plug region
17
.
As shown in
FIG. 2B
, the V-pnp has an n-type buried layer
20
at the surface layer of the p-type semiconductor substrate
1
on which a p-well comprised of a p-type collector region
21
is formed. Due to the n-type buried layer
20
, the p-type collector region
21
and the p-type semiconductor substrate
1
are separated electrically. At the surface layer of the p-type collector region
21
are formed an n-type base region
22
and a graft base
22
a
connected to the base region
22
. At the surface layer of the n-type base region
22
is formed a p-type emitter region
23
. Also, the surface layer of the p-type collector region
21
is formed with a collector take-out part
24
separate from the n-type base region
22
and graft base
22
a
. The collector take-out part
24
contains a p-type impurity at a higher concentration than the p-type collector region
21
.
On the n-type epitaxial layer
2
or LOCOS
3
is formed for example a silicon oxide film
9
as a first insulating film. In the silicon oxide film
9
on the base take-out part, p-type emitter region
23
, and collector take-out part
24
are formed openings. At the opening on the p-type emitter region
23
is formed an emitter take-out electrode
25
comprised of p-type polysilicon. In the same way, at the opening on the collector take-out part
24
is formed a collector take-out electrode
26
comprised of p-type polysilicon. Electrodes
13
are formed on the base take-out part, emitter take-out electrode
25
, and collector take-out electrode
26
.
As shown in
FIG. 3A
, the S-pnp has a p-type collector region
21
in the n-type epitaxial layer
2
. A part of the p-type collector region
21
reaches the surface of the p-type semiconductor substrate
1
. Also, in the n-type epitaxial layer
2
are formed an n-type base region
22
and a graft base
22
a
. A part of the n-type base region
22
is formed on the p-type collector region
21
. At the surface layer of the n-type base region
22
on the p-type collector region
21
is formed a p-type emitter region
23
. Also, at the surface layer of the p-type collector region
21
is formed a collector take-out part
24
. The collector take-out part
24
contains a p-type impurity at a higher concentration than the p-type collector region
21
.
On the n-type epitaxial layer
2
or LOCOS
3
is formed for example a silicon oxide film
9
as a first insulating film. In the same way as the V-pnp shown in
FIG. 2B
, the silicon oxide film
9
on the base take-out part, p-type emitter region
23
, and collector take-out part
24
are provided with openings. At the opening on the p-type emitter region
23
is formed an emitter take-out electrode
25
comprised of p-type polysilicon. In the same way, at the opening on the collector take-out part
24
is formed a collector take-out electrode
26
comprised of p-type polysilicon. Electrodes
13
are formed on the base take-out part, emitter take-out electrode
25
, and collector take-out electrode
Depke Robert J.
Eckert George
Fenty Jesse A.
Holland & Knight LLP
Sony Corporation
LandOfFree
Semiconductor device and process of production of same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and process of production of same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and process of production of same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3361205