Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-05-12
2002-06-25
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S192000, C257S195000, C257S020000, C257S024000, C257S155000, C257S029000, C257S189000, C257S190000, C438S167000, C438S172000, C438S285000, C438S571000, C438S590000
Reexamination Certificate
active
06410947
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a process of production of the same, more particularly relates to a hertero-junction filed effect transistor applicable to a microwave communications device and a process of production of the same.
2. Description of the Related Art
In recent years, in cellular phone and other mobile communications system, miniaturization and reduction of power consumption of terminals have been strongly sought. Therefore, the transistors and other devices used for terminals have been miniaturized and reduced in power consumption. For example, ICs for power amplifiers used for digital cellular phones, now becoming the mainstream in mobile communications are being required to operate with a single positive power source, be driven by a lower voltage, and operate at a higher efficiency.
One of the devices used for power amplifiers is the hetero-junction field effect transistor (HFET). The currently mass produced HFETs use electrons as carriers and are often called “high electron mobility transistors” (HEMTs). In HEMTs, the hetero-junction formed between the layer in which the electrons run (channel layer) and the layer supplying the electrons (doping layer) is used for current modulation.
HFETs differ in channel structure from conventional junction FETs or Schottky junction field effect transistors (MESFETs; metal semiconductor FETs). In HFETs, carriers are stored in the channel layer by supplying a positive voltage to the gate electrodes. Therefore, HFETs are characterized by a superior linearity of a gate-source capacitance C
gs
and mutual conductance G
m
to a gate voltage V
g
good compared with JEFTs, MESFETs, and other devices. This characteristic of HFETs is advantageous for improving the efficiency of a power amplifier.
FIG. 3
is a cross-sectional view of an example of the configuration of an HFET. In the HFET shown in
FIG. 3
, a first barrier layer
33
, a channel layer
34
, and a second barrier layer
35
are sequentially stacked on a semi-insulating GaAs substrate
31
via a buffer layer
32
comprised of a semi-insulating GaAs single crystal.
The first barrier layer
33
is for example made of an A
1
GaAs or other III-V compound semiconductor and is structured as a carrier supply region
33
a
containing an n-type impurity sandwiched between high resistivity layers
33
b
,
33
b′
. As the material of the channel layer
34
, a semiconductor having a smaller bandgap than the first barrier layer
33
and the second barrier layer
35
, such as InGaAs, is used. The second barrier layer
35
is for example made of A
1
GaAs or another compound semiconductor and is structured as a carrier supply region
35
a
containing an n-type impurity sandwiched between high resistivity layers
35
b
,
35
b′
.
Cap layers
36
formed on the second barrier layer
35
, and the cap layers
36
are covered with an insulating layer
37
comprised of for example a silicon nitride film. A source electrode
38
and a drain electrode
39
are formed I contact holes formed in the insulating layer
37
. Also, gate electrode
40
is formed on the second barrier layer
35
. When applying voltage to the gate electrode
40
, the current between the source electrode
38
and the drain electrode
39
is modulated.
Generally, in HFETs, as shown in
FIG. 3
, a recess structure in which a thickness of the second barrier layer
35
is made thinner near the gate
40
is often employed. When the recess structure is employed, carriers in the channel layer
34
below the gate electrode
40
become easier to deplete.
Further, an HFET of a structure shown in
FIG. 4
has also been recently proposed. In the HFET shown in
FIG. 4
, there is no recess as shown in
FIG. 3
below the gate electrode
40
, but a p-type low resistivity region
41
containing a p-type impurity is formed. The p-type low resistivity region
41
contacts the gate electrode
40
and is formed buried in the second barrier layer
35
. The rest of the parts are the same as in the structure of the HFET shown in FIG.
3
.
The p-type low resistivity region
41
is formed by diffusing a p-type impurity, for example, Zn, at a high concentration (for example 1=10
19
atoms/cm
3
) in part of the second barrier layer
35
, specifically, the high resistivity layer
35
b′.
In the case of the structure shown in
FIG. 4
, a pn junction is formed below the gate electrode
40
. Therefore, a built-in voltage is made larger compared with the case where a Schottky contact is formed at the gate electrode part as shown in FIG.
3
and it is made possible to supply a higher positive voltage to the gate electrode. Due to this, operation with a single positive power source is enabled and a negative power source circuit becomes unnecessary. Also, in the case of the structure shown in
FIG. 4
, the good linearity of the mutual conductance G
m
and the gate-source capacitance C
gs
to the gate voltage V
g
characteristic of HFETs remains.
Summarizing the problems to be solved by the invention, in the case of the conventional HFET shown in
FIG. 3
, the second barrier layer
35
below the gate electrode
40
is etched and a threshold voltage of the transistor is adjusted by the depth of the recess formed by etching. However, it is generally difficult to control the etching amount precisely in etching for forming the recess and the etching amount readily becomes uneven. As a result, the threshold voltage readily becomes uneven.
Also, in the conventional HFET shown in
FIG. 4
, the gate electrode is joined with the p-type low resistivity region
41
formed buried in the second barrier layer
35
. Usually, as the material for the gate electrode, a multilayer structure metal comprised of Ti/Pt/Au stacked sequentially from the junction interface is often used. When the compound semiconductor joined with the gate electrode is for example p-type GaAs, a relatively good ohmic contact can be obtained.
However, generally, in the case of for example A
1
GaAs and other semiconductors having a larger bandgap than GaAs, it is difficult to incorporate a p-type impurity at a high concentration and it becomes difficult to obtain a good ohmic contact with the above usual gate electrode material. As a result, the contact resistance between the gate electrode and the semiconductor below the gate electrode increases and causes a decline of the high-frequency characteristics.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device able to operate with a single positive power source, able to be reduced in power consumption by improving efficiency, and improved in high-frequency characteristics by lowering the resistance of a gate contact and a process of production of the same.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a carrier run layer formed on a substrate for running of carriers; a carrier supply layer formed on the carrier run layer, having a larger bandgap than the carrier run layer, and containing a first conductivity type impurity; a barrier layer formed on the carrier supply layer and having a smaller bandgap than the carrier supply layer; a source electrode and a drain electrode formed on the barrier layer at a predetermined distance from each other; a gate electrode formed on the barrier layer between the source electrode and the drain electrode away from the source electrode and the drain electrode; and a first low resistivity region formed at least below the gate electrode in the barrier layer and containing a second conductivity type impurity opposite in conductivity to the first conductivity type.
Preferably, a first high resistivity layer having a larger bandgap than the semiconductor comprising the carrier run layer and comprised of an undoped semiconductor is formed between the carrier supply layer and the barrier layer.
More preferably, the device further comprises a second low resistivity layer formed below the first low resistivity region in the f
Kang Donghee
Sonnenschein Nath & Rosenthal
Sony Corporation
Thomas Tom
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