Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-04-18
2003-01-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S508000, C257S520000, C257S524000, C257S621000, C257S758000
Reexamination Certificate
active
06504229
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2000-121220 filed on Apr. 21, 2000, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a process of manufacturing the semiconductor device. In particular, it relates to a semiconductor device provided with minuscule through holes formed by dry etching and a process of manufacturing the semiconductor device.
2. Description of Related Art
In a step of dry etching performed on an insulating film or a conductive film in the manufacture of a semiconductor device, a phenomenon called “charging” occurs, i.e., extremely high electric potential is partially applied due to charge migration within a wafer. The charging is caused by non-uniformity of plasma utilized as an etchant leading to variation of an amount of ions injected in a wafer surface.
In the current situation, the charging is remarkably problematic since a low pressure (e.g., 0.01 to 0.1 mTorr) and high density plasma source such as ECR (electron cycletron resonance), helicon, helios and the like is coming into common use for the purpose of further miniaturization.
The charging in the wafer may possibly damage a gate oxide film of transistors formed by a series of manufacturing steps, which deteriorates reliability of the semiconductor device.
Further, there is a tendency to form much thinner gate oxide film in accordance with the miniaturization of the semiconductor device, which seriously promotes the damage caused by the charging.
Therefore, various examinations have been conducted on the mechanism of how the damage is caused by the charging and on measures of alleviating the damage. Further, evaluation with respect to Q
BD
, TDDB (time dependent dielectric breakdown), hot carriers and the like has been performed with various antenna patterns to examine the occurrence of the gate breakdown. From the results thereof, currently employed is a prevention of the gate breakdown by giving a limitation to the antenna ratio according to the designing rule at a stage of designing the semiconductor device.
However, the damage due to the charging has not actually been alleviated very much. Under the present circumstances, charging which does not lead to the gate breakdown and that accumulates in a floating gate are not questioned.
The charging which does not lead to the gate breakdown may possibly vary contact resistance in via holes formed by dry etching, or raise the resistance in a certain via hole.
For example, where a metal floating structure underlies the insulating layer, reaction products may remarkably be deposited or accumulated through the etching or the etching rate of the insulating layer to the underlying structure may be varied as compared to the case where the underlying structure is not floating. It is known that the etching rate of the insulating layer to the underlying structure is varied in accordance with an area of the underlying metal floating structure or an amount of charges accumulated in the metal floating structure.
Accordingly, if the charging occurs in the underlying metal structure or the like in the case where a plurality of contact holes or via holes have been simultaneously formed under the same conditions, the etching rate of the insulating film may increase depending on the kind and the size of the underlying structure. Further, reaction products are partially deposited in the holes, which leads to poor conduction at the holes and increase of the hole resistance.
To deal with such a problem, means of decreasing the etching rate of the insulating film to the underlying structure has conventionally been employed, for example, by reducing an amount of easily depositing gas (C
4
F
8
, CH
2
F
2
and the like) or increasing an amount of diluent gas such as Ar and He to decrease a partial pressure of the easily depositing gas and reduce the deposition of reaction products.
However, the decreased etching rate causes over-etching of the underlying structure and increases loss of the underlying structure, which is problematic since a processing margin is reduced.
Under such circumstances, it has been required an alternative method of forming the via holes or the contact holes by dry etching while preventing the deposition and the accumulation of reaction products, as well as the variation of the etching rate which will cause poor conduction and high hole resistance.
SUMMARY OF THE INVENTION
The present invention has been achieved in view of the above-mentioned problem. An objective of the present invention is to provide a process of manufacturing a semiconductor device capable of forming the via holes by dry etching while preventing the deposition and the accumulation of the reaction products, the variation of the etching rate and the reduction of the processing margin, as well as the semiconductor device itself.
According to the present invention, provided is a semiconductor device comprising a first insulating film, a wiring layer and a second insulating film formed in this order on a semiconductor substrate, the second insulating film being provided with one or more through holes formed onto the wiring layer, wherein the wiring layer is electrically isolated by the first insulating film and the second insulating film at a region other than a region where the through holes are formed, and a ratio between a total of a bottom area of the through holes formed onto the wiring layer and a top surface area of the wiring layer is 1:300 to 10,000.
Still according to the present invention, provided is a process of manufacturing a semiconductor device comprising: forming a first insulating film on a semiconductor substrate; forming an electrically floating wiring layer on the first insulating film; forming a second insulating film on the wiring layer; and forming one or more through holes in the second insulating film onto the wiring layer so that a ratio between a total of a bottom area of the through holes and a top surface area of the wiring layer is 1:300 to 10,000.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5192988 (1993-03-01), Yoshii
patent: 5258329 (1993-11-01), Shibata
patent: 5409861 (1995-04-01), Choi
patent: 5874358 (1999-02-01), Myers et al.
patent: 6207566 (2001-03-01), Chang
patent: 6319844 (2001-11-01), Usami et al.
Yonekura et al.: “Effects of Charge Build-up of Underlying Layer by High Aspect Ratio Etching” Jpn. J. Appl. Phys. vol. 37 (1988) pp. 2314-2320, Part 1, No. 4B, Apr. 1998.
Satoh Masayuki
Yamauchi Hiroshi
Flynn Nathan J.
Forde Remmon R.
Sharp Kabushiki Kaisha
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