Semiconductor device and process for formation thereof

Details Semiconductor device and process for formation thereof Semiconductor device and process for formation thereof

1995-01-23

1996-12-10

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 29, 437 69, H01L 21265, H01L 21302, H01L 21304, H01L 2176

Patent

active

055830641

ABSTRACT:
A recess is formed (dug) into the surface of a substrate to form a gate channel in the recess, so that a monocrystalline source/drain region can be formed at a level higher than that of the channel. The process includes the steps of: (a) forming an insulating layer and an oxidation preventing layer on a semiconductor substrate, and removing the oxidation preventing layer of a channel region of the transistor by an etching process; (b) forming an oxide layer on the channel region of the transistor by thermally oxidizing the semiconductor substrate, removing the oxidation preventing layer, and carrying out a first ion implantation on the whole surface; (c) removing the oxide layer, and forming the channel of the transistor in the form of a recess so as for the recess to be positioned lower than the surface of the substrate; (d) forming a gate electrode in the recess; and (e) carrying out a second ion implantation on the whole surface, and carrying out a heat treatment to form a source/drain region.

REFERENCES:
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patent: 5108937 (1992-04-01), Tsai et al.
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patent: 5342796 (1994-08-01), Ahn et al.
patent: 5371024 (1994-12-01), Hieda et al.
J. E. Moon, et al.; "A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS)"; vol. 11, No. 5, May 1990; pp. 221-223.
James R. Pfiester, et al.; "A Self-Aligned Elevated Source/Drain MOSFET"; vol. 11, No. 9, Sep. 1990; pp. 365-367.
Shigeo Onishi, et al.; "Formation of a Defect-Free Junction Layer by Controlling Defects Due to As.sup.+ Implantation"; IEEE/IRPS 1991; pp. 255-259.
Eiji Takeda, et al.; "New Grooved-Gate MOSFET with Drain Separated from Channel Implanted Region (DSC)"; IEEE 1983; pp. 681-686.
K. Sunouchi, et al.; "Double LDD Concave (DLC) Structure for Sub-Half Michon Mosfet"; IEDM 88; pp. 226-229.

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