Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2001-02-06
2004-02-24
Wilson, Allan R. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S692000, C257S777000, C257S778000, C257S782000, C257S797000
Reexamination Certificate
active
06696751
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing same, and more particularly, to a semiconductor device comprising a semiconductor element(s) and a package on which these semiconductor elements are mounted.
2. Description of the Related Art
In recent years, with market demands for compactification and weight reduction with respect to electronic devices, or portable devices in particular, there has been especially strong requirement for reduction in the size and weight of semiconductor devices. In a conventional single chip package, when positioning and mounting an LSI chip (or semiconductor element), it is customary for the centre of the LSI chip (or semiconductor element) to be aligned with the centre of the chip mounting region on the package. This is because emphasis is given to the uniformity of the semiconductor device on which the single chip package and LSI chip are positioned and mounted, and in practice, there has been little occurrence of physical imbalance in the vertical or lateral directions, and this has helped to achieve a stabilized product quality.
However, since uniformity is emphasized in this manner, in cases where it is required, for whatever reason, to provide expansion outside the single chip package in a region or regions which face one to three edges (several locations) of the chip package, a method has been adopted whereby the other regions thereof are expanded in an equal fashion, in order to maintain uniformity (line symmetry and point symmetry). In other words, as illustrated in
FIG. 3
, in a case where, for whatever reason, the need arises to expand a region
6
having a distance d
1
in the direction of the arrow a, outside of one edge of a single chip package
2
having an LSI chip
1
mounted in the centre thereof, according to the existing concept, expansion is not only performed in this single direction, but also in the regions outside the other three edges thereof by the same distance d
1
from the original single chip package
2
, provided that the single chip package
7
permits the expansion region
6
, as illustrated in FIG.
4
. Moreover, in a multi-chip module (MCM) whereon a plurality of chips are mounted, the chips are disposed and mounted in a uniform fashion on the MCM package, in order to maintain uniformity (line symmetry and point symmetry).
Therefore, in the case of either a single chip package or a multi-chip module (MCM), there has been a problem in that, in its ultimate form, the semiconductor device is enlarged unnecessarily, in order to maintain uniformity (line symmetry, point symmetry).
SUMMARY OF THE INVENTION
With the foregoing in view, it is an object of the present invention to avoid unnecessary enlargement of semiconductor devices, by providing a semiconductor device having improved geometrical relationships between a semiconductor chip and a semiconductor chip mounting region of a package.
Thorough research into methods for providing a semiconductor device having improved geometrical relationships between semiconductor chips and the semiconductor chip mounting regions of a package has been conducted.
As a result of this research, it was discovered: that the aforementioned uniformity means point symmetry, line symmetry and equidistant spacing (for example, the semiconductor elements are disposed in an equidistantly spaced manner), and the like; and that the reason that uniformity of this kind is emphasized is that there is a firm belief that it is advantageous in terms of workability and device operating characteristics in the manufacturing processes for semiconductor devices and electronic products using same, and there is no merit in consciously discarding this uniformity. There is also a reason that if uniformity is impaired, distortion may occur in the semiconductor device, leading to problems of assembly errors, or performance faults, or the like, in the various manufacturing stages leading up to completion of an electronic product.
To add to the above, it was also discovered that if uniformity was disregarded, rather than being emphasized, then especially in cases where a plurality of semiconductor elements are mounted on a semiconductor device, merits are obtained in that greater freedom is gained with regard to combinations of sizes and introduction of multiple-stage bonding arrays becomes possible, and provided that the size of the semiconductor elements themselves is within a certain size, the problem of distortion can be substantially resolved, and hence the present invention has been established. The beneficial effects of the present invention are particularly notable in cases where the size of the semiconductor device is 19 mm×19 mm or smaller, and the number of semiconductor elements mounted thereon is between 1-4.
More specifically, the present invention is as follows.
1. A semiconductor device comprising a package having: a mounting region for mounting at least one semiconductor element; a first region containing the above-described mounting region and substantially sharing point symmetry with the above-described mounting region, wherein the width of the portions of the first region not including the above-described mounting region is substantially uniform; and a second region provided at a perimeter edge of the above-described first region and not substantially sharing point symmetry with the above-described mounting region.
2. The semiconductor device described in 1 above, wherein there exist a plurality of second regions which are not mutually contacting.
3. The semiconductor device described in 1 above, wherein the above-described mounting region and the above-described second region substantially share line symmetry.
4. The semiconductor device described in 1 above, wherein the above-described second region contacts two or more edges of the above-described first region.
5. The semiconductor device described in 1 above, comprising at least one connecting means between the above-described first region and the above-described semiconductor element.
6. The semiconductor device described in 1 above, wherein the above-described first region and the above-described second region are formed in different planes.
7. The semiconductor device described in 1 above, wherein the above-described semiconductor element is mounted on the mounting region by a flip chip bonding, under-fill resin is filled into the gap between the above-described semiconductor element and the above-described mounting region, and a region for supplying the above-described under-fill resin is formed in the above-described second region.
8. The semiconductor device described in 1 above, wherein first bonding pads are disposed in the above-described first region, second bonding pads are disposed in the above-described second region, respectively, and first lead wires and second lead wires leading from the above-described semiconductor element are connected respectively to the above-described first and second bonding pads.
9. The semiconductor device described in 8 above, comprising the first bonding pads and the second bonding pads disposed in an alternating zigzag pattern.
10. A portable device containing the semiconductor device described in any one of 1 to 9 above.
11. A method for manufacturing the semiconductor device described in 1 above, comprising the steps of: mounting the above-described semiconductor element on the mounting region by means of a flip chip bonding; supplying under-fill resin to the above-described second region; and causing the above-described under-fill resin in the second region to move to the above-described first region and fill into the gap between the above-described semiconductor element and the above-described mounting region.
12. A method for manufacturing a semiconductor device described in 1 above, comprising the steps of: arranging first bonding pads in the above-described first region; arranging second bonding pads in the above-described second region; and connecting first and second lead wires derive
Iida Kenji
Kajiki Atsunori
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
Warren Matthew E.
Wilson Allan R.
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