Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2000-02-04
2004-09-07
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S635000, C257S637000, C257S644000, C257S650000, C257S528000, C257S529000, C257S530000
Reexamination Certificate
active
06787886
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device, such as a semiconductor integrated circuit device, having Spin On Glass film (it is called hereinafter SOG film) that is suitable for multilevel interconnection structure to achieve high integration and a method of fabricating thereof. This application is a counterpart of Japanese patent application, Serial Number 192584/1999, filed Nov. 7, 1999, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In a multilevel interconnection technique of a semiconductor device, a multilevel interconnection structure can be obtained by forming an interlevel insulator between a lower wiring and an upper wiring, wherein the lower wiring is formed over a semiconductor substrate and the upper wiring is formed over the lower wiring. An integration of the semiconductor device can be improved by the multilevel interconnection structure.
In general an electrical junction part is formed in a contact hole which is provided in the interlevel insulator so as to expose an active region of the semiconductor substrate.
There is a self-alignment contact technique to provide such contact hole. This self-alignment technique is executed by following steps.
First, a pair of gate electrodes whose side surfaces and upper surfaces are covered with protection films, e.g., a silicon nitride film, is formed over a semiconductor substrate.
Next, an interlevel insulator is formed over the entire surface of the semiconductor substrate so as to cover the gate electrodes and the protection films.
Next, an etching mask having an opening is formed on a surface of the interlevel insulator so that the opening corresponds to an active region of the semiconductor substrate between the gate electrodes.
Then, an etching process is executed by using the etching mask to form a contact hole extending from the active region to an upper surface of the interlevel insulator. At this time, since the protection films have a high etching-resistance characteristic against an etching gas, or the like, the protection films are prevented from being etching. This means that the protection films function as an etching mask.
In the self-alignment contact technique, even though the etching mask is formed on a position which is slightly different from a desired position, the contact hole exposing the active region can be obtained because of a mask function of the protection film.
However, an anisotropic etching is used for a selective etching process using the etching mask wherein the anisotropic etching is an etching that an etching rate in a direction horizontal is relatively smaller than the etching rate in a direction vertical. Therefore, when a large amount of mask misalignment occurs, there is a possibility that an area of the exposed active region become smaller than an area having a desired value.
The reduction of the exposed active region causes an increase in the contact resistance between the exposed active region and a conductive part which is formed within the contact hole. This means also that electrical characteristics become uneven among contact holes.
In order to overcome such problems mentioned above, an idea that an isotropic etching is used for the selective etching instead of the anisotropic etching may arise. However, when only the isotropic etching is simply applied to the selective etching to form the contact hole in the interlayer insulator, it is difficult to control the area of the exposed active region and the depth of the contact hole. This means that a required contact hole is not obtained.
Another idea that both of the isotropic etching and the anisotropic etching is applied to the selective etching may also arise. However, it is not realistic that the interlayer insulator having single etching-resistance property is subjected to different kinds of etching methods, i.e., the isotropic etching and the anisotropic etching.
Consequently, there has been a need for a semiconductor device having improved electric characteristics and a method of fabricating the same.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a semiconductor device and a method of fabricating the same that may improve electric characteristics among contact holes formed therein.
It is another object of the present invention is to provide a semiconductor device and a method of fabricating the same that may improve a moisture absorption property.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor device which includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of a SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer and is formed over the MOS transistor and wherein the surface layer is denser than the base layer.
According to another aspect of the present invention, for achieving one or more of the above objects, there is provided a method of fabricating a semiconductor device which includes forming a SOG layer over a MOS transistor formed on a semiconductor substrate; converting a surface portion of the SOG layer into to a dense layer which is denser than a bottom portion of the SOG layer, removing a first portion of the dense layer to expose a surface of the bottom portion of the SOG layer by a first etching, removing a second portion which corresponds to the exposed surface of the bottom portion of the SOG layer to expose a diffusion region of the MOS transistor by a second etching, and forming a conductive material within a space in which the first and second portions are removed.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
REFERENCES:
patent: 5716872 (1998-02-01), Isobe
patent: 5808363 (1998-09-01), Watanabe
patent: 5903041 (1999-05-01), La Fleur et al.
patent: 6246105 (2001-06-01), Morozumi et al.
patent: 1-208831 (1989-08-01), None
patent: 06021095 (1994-01-01), None
patent: 08046044 (1996-02-01), None
patent: 09069562 (1997-03-01), None
Sorab K. Ghandhi; “VLSI Fabrication Principles, Silicon and Gallium Arsenide” (Second Edition); Copyright 1994; p. 528 and p. 725; A Wiley-Interscience Publication, John Wiley & Sons, Inc.
Asakawa Kazuhiko
Shimizu Wataru
Louie Wai-Sing
Pham Long
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