Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1998-08-27
2003-03-25
Chaudhuri, Olik (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S623000, C257S635000, C257S758000, C257SE29162
Reexamination Certificate
active
06538301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and a manufacturing method of a semiconductor device such as a dynamic RAM.
2. The Related Art
Nowadays, in order to make a flat surface regarding a semiconductor device, a SOG (SPIN on GLASS) film is used. The SOG film is formed by introducing SOG material on the surface of the semiconductor wafer which is spinning, and flowing the SOG material from the central to the peripheral of the semiconductor wafer. Further, due to the integration, multi-layer interlayer insulating film structure is used. In such a structure, a metal wiring layer is used for preventing the edge of the multi-layer insulating films from peeling off each other. Such a device using the SOG film and the metal wiring layer is explained as follows, with reference to
FIGS. 4A
to
4
H.
FIGS. 4A
to
4
H are sectional views for explaining a manufacturing process of a semiconductor device of the related art. As shown in
FIG. 4A
, a field oxidation film
2
is formed in a chip region
13
to create an element formation region on a surface of a substrate
1
, for example, by selective oxidation (LOCOS: Local Oxidation of Silicon). A scribe line region
12
is a cutting region necessary for dicing a semiconductor wafer into separate chips.
After the field oxidation film
2
has been formed, subsequently, as shown in
FIGS. 4B
to
4
D, interlayer insulating films,
3
to
5
, are sequentially formed by, for example, a CVD method so as to cover the entire of the substrate
1
on which the field oxidation film
2
has been formed. Although omitted here, wiring layers and element films are formed between the respective interlayer insulating films. Thereafter, as shown in
FIG. 4E
, a resist is applied to the entire surface, and is exposed and developed to form a resist pattern
6
. Then the respective interlayer insulating films,
3
to
5
, are etched by using the resist pattern
6
as a mask to form an opening portion
7
and patterned interlayer insulating films,
3
′ to
5
′.
After the opening portion
7
has been formed and the resist pattern
6
has been removed, subsequently, as shown in
FIG. 4F
, metal material, for example, aluminum (Al) is deposited on the entire surface by, for example, a sputtering method, and it is selectively etched by RIE (reactive Ion Etching) to form a metal wiring layer
8
. The metal wiring layer
8
is formed to prevent peeling of end portions of the respective interlayer insulating films
3
′ to
5
′. Thereafter, as shown in
FIG. 4G
, an insulating film
9
, for example, an oxide film is formed by, for example, a CVD method, so as to cover the entire surface.
After the insulating film
9
is formed, subsequently, as shown in
FIG. 4H
, a SOG (SPIN on GLASS) film
10
is formed on the entire surface by a spin coating method. In the drawing, an arrow Z denotes a flow of, for example, silicon dioxide at the time when the SOG film is formed by applying silicon dioxide (such a flow of silicon dioxide will be hereinafter referred to as flow of SOG). Thereafter, by using the selective ratio of the SOG film and the oxide film, surface flattening is carried out by a dry etch-back treatment.
In recent years, to increase the degree of integration, in a semiconductor device such as a dynamic RAM, a device element has been disposed on a peripheral portion of a chip region which historically has not been used as a device region. For example, as illustrated in
FIGS. 5A and 5B
, a through hole
200
is attempted to be formed in the interlayer insulating films
3
to
5
on the peripheral portion. As a result, in the manufacturing method described above, the following problems have began to occur.
In the manufacturing method, after the metal wiring layer
8
is formed so as to cover the end portions of the interlayer insulating films over the entire circumference of the chip region, the SOG film
10
is formed by applying a spin coating. In this case, since the surrounding portion where the metal wiring layer has been formed is higher, the flow of SOG is blocked by the stepped portion. Thus, as shown in
FIGS. 5A and 5B
, a thick SOG is accumulated in the vicinity of a corner portion of the metal wiring layer (which means that, for example, when silicon dioxide is applied to form a SOG film, thick silicon dioxide is accumulated), so that a SOG puddle
100
is formed. If the SOG puddle
100
forms, since the SOG puddle
100
is not completely etched back and remains when the surface is flattened, flattening damaged may occur. Moreover, when the SOG puddle
100
can not be completely etched back and some bump remains, for the through hole forming a contact hole
200
, for making contact with a wiring layer just below that portion, can not be opened completely and the contact can not be properly made to the wiring layer.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device which can prevent SOG from thickly accumulating in the vicinity of a corner portion of a metal wiring layer used to prevent the edge of multi-layer interlayer insulating films on the chip edge from peeling off.
A semiconductor device of the present invention comprises: a semiconductor substrate; an interlayer insulating film formed over the semiconductor substrate; and a metal wiring layer formed so as to cover an end portion of the interlayer insulating film over the periphery of an element formation region of the semiconductor substrate, the metal wiring layer having at least one cut portion formed at the vicinity of a corner of the element formation region.
A semiconductor device of the present invention comprises: a semiconductor substrate having at least a recess located in the vicinity of a corner of an element formation region; a first interlayer insulating film formed over the element formation region of the semiconductor substrate; a second interlayer insulating film formed to cover from the first interlayer insulating film over the element formation region to the semiconductor substrate exposed by the recess; and a metal wiring layer covering an end portion of the second interlayer insulating film, the metal wiring layer having an end portion formed on the interlayer insulating film in the recess.
A method of manufacturing a semiconductor device of the present invention, comprises the steps of:
forming at least one interlayer insulating film over a semiconductor substrate, the interlayer insulating film having an end portion in the vicinity of an element formation region of the semiconductor substrate;
forming a metal wiring layer so as to cover the end portion of the interlayer insulating film, the metal wiring layer having at least one cut portion in the vicinity of a corner of the element formation region; and
forming, by spin coating, an insulating film on the surface of the semiconductor substrate so that material of the insulating film flows out through the cut portion.
A method of manufacturing a semiconductor device of the present invention, comprises the steps of:
forming a field insulating film in an element formation region of a surface of a semiconductor substrate;
forming a first interlayer insulating film on the field insulating film;
removing the field insulating film and the first interlayer insulating film in vicinity of a boundary of a scribe line region and the element formation region to form a cavity in vicinity of the boundary of the scribe line region and the element formation region;
forming a second interlayer insulating film to cover from on the element formation region to on a surface of the semiconductor substrate exposed by the cavity;
forming a metal wiring layer so as to cover an end portion of the interlayer insulating film, the metal wiring layer having an end portion which is on the second interlayer insulating film formed over a surface of the semiconductor substrate exposed by the cavity; and
forming an insulating film over the second interlayer insulating fil
Kimura Atsushi
Yamada Naoto
Yoshida Naoyuki
Chaudhuri Olik
Kebede Brook
NEC Corporation
Sughrue & Mion, PLLC
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