Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2003-08-04
2004-11-16
Tokar, Michael (Department: 2829)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S770000
Reexamination Certificate
active
06818525
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor devices and, more particularly, to integrated circuits having components formed on a low capacitance region of a semiconductor die.
Semiconductor technology continues to scale transistors to have smaller dimensions in order to provide increased functionality and a higher frequency capability. For example, wireless communication devices often use integrated circuits that include high density digital signal processing functions on the same die as analog circuits operating at frequencies in excess of five gigahertz.
However, some integrated circuit components, such as passive devices, are not readily scalable. These devices have relatively high parasitic substrate capacitances, which often limits the overall frequency capability of an integrated circuit. For example, inductors are not easily reduced in size without reducing their quality factor or inductance to an unacceptable level, and bonding pads are not scalable because of the need to attach wire bonds to the bonding pads.
A variety of techniques have been tried to reduce the parasitic capacitances of passive integrated circuit components. One such technique is to form the components over a low permittivity material. However, current low permittivity materials are limited to film thicknesses that are too thin to produce an adequate reduction in parasitic capacitance. Another approach is to form the components over a thick dielectric film in which are formed air gaps or voids that reduce the overall permittivity of the dielectric film. However, previous films made with such voids introduce substantial stress in a semiconductor substrate, which degrades the performance and reliability of the integrated circuit. Other schemes reduce the stress by producing fewer voids or voids with only a limited volume, which has a correspondingly limited effect on parasitic capacitance. Another issue with previous art has been the high costs associated with the complex patterning and etching steps to produce isolation structures with large void to pillar ratios.
Hence, there is a need for a low capacitance structure and method of making a semiconductor device that maintains a low cost while reducing die stress and avoiding the introduction of contaminants into the integrated circuit.
REFERENCES:
patent: 5240875 (1993-08-01), Tsou
Durham James A.
Kamekona Keith
Schoonover Brian
Semiconductor Components Industries L.L.C.
Stipanuk James J.
Tokar Michael
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