Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2002-05-20
2003-11-11
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S750000, C257S692000
Reexamination Certificate
active
06646357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of production of the same, more particularly relates to a semiconductor device produced by forming external connection terminals on an electrode formation surface of a semiconductor wafer and a method of production of the same.
2. Description of the Related Art
FIGS. 12A
to
12
I show a method of production of a semiconductor device formed with metal posts as external connection terminals on an electrode formation surface of a semiconductor wafer. In this method of production, first, an electrode formation surface of a semiconductor wafer
10
from which electrodes
12
are exposed and which is covered by a passivation film
14
(
FIG. 12A
) is covered with a conductive layer
16
by sputtering (FIG.
12
B). Next, the surface of the conductive layer
16
is covered by a photosensitive resist
18
(FIG.
12
C), then the photosensitive resist
18
is exposed and developed to expose portions for forming interconnection patterns at the surface of the conductive layer
16
(FIG.
12
D).
The electrodes
12
are arranged at an extremely high density at for example the periphery of the electrode formation surface of the semiconductor wafer
10
. As shown in
FIG. 12E
, the interconnection patterns
20
are formed by electroplating the exposed surfaces of the conductive layer
16
by copper. The interconnection patterns
20
are formed led out from the electrodes
12
so as to secure spaces for arrangement of the external connection terminals.
Next, the photosensitive resist
18
is removed and the surfaces of the interconnection patterns
20
and conductive layer
16
are covered by a dry film
22
(FIG.
12
F), This dry film
22
is for forming the copper posts
24
forming the external connection terminals (FIG.
12
G). The dry film
22
is exposed and developed to form holes for plating at portions for forming the copper posts
24
on the interconnection patterns
20
. By electroplating these portions by copper, copper is built up in the plating holes and metal posts
24
of heights of about 100 &mgr;m are formed. Next, the surfaces of the copper posts
24
are successively plated by nickel, palladium, etc. to form the barrier layers
26
.
The dry film
22
is removed, then the portions of the conductive layer
16
exposed at the electrode formation surface are removed by etching (FIG.
12
H). In this way, the electrode formation surface of the semiconductor wafer
10
is formed with copper posts
24
electrically connected with the electrodes
12
through the interconnection patterns
20
.
Next, as shown in
FIG. 12I
, the electrode formation surface of the semiconductor wafer
10
is covered with a resin
28
for sealing. The resin
28
is formed to substantially the same thickness as the copper posts
24
. The end faces of the copper posts
24
are exposed at the surface of the resin
28
. After the resin sealing, solder balls are placed on the surfaces of the barrier layers
26
and the solder made to reflow to form solder bumps (not shown). Finally, the semiconductor wafer
10
can be diced along with the resin
28
to obtain chip-sized semiconductor devices.
FIGS. 13A
to
13
I show another method for producing a chip-sized semiconductor device. The semiconductor device obtained by this method of production has gold wires bent in L-shapes for use as external connection terminals. The steps shown in
FIGS. 13A
to
13
E are basically no different from the steps shown in the above
FIGS. 12A
to
12
E. In this method, however, the interconnection patterns
20
are not sealed by resin. The interconnection patterns
20
are formed by gold plating so as to enable them to be left as they are exposed at the outside surface of the semiconductor device.
As shown in
FIG. 13F
, the photosensitive resist
18
(
FIG. 13E
) is removed. Next, as shown in
FIG. 13G
, the electrode formation surface is covered by a resist, then holes
30
a
are formed in the interconnection patterns
20
at portions for later bonding of the gold wires. The electrode formation surface is covered by the resist
30
so as to cover only the outer surfaces of the gold wires with reinforcement plating after bonding the gold wires. As shown in
FIG. 13H
, the gold wires are bonded to the interconnection patterns
20
in register with the openings
30
a
(FIG.
13
G). Next, the gold wires are bent into L-shapes and the ends thereof are cut off to form the external connection terminals
32
. The outer surfaces of the gold wires are plated to reinforce the wires (the plating material is not shown in the drawing), then the resist
30
is removed and, as shown in
FIG. 13I
, the exposed portions of the conductive layer
16
are removed by etching.
In this way, the electrode formation surface of the semiconductor wafer
10
is formed with external connection terminals
32
electrically connected with the electrodes
12
through the interconnection patterns
20
. Finally, the semiconductor wafer
10
is diced to obtain semiconductor devices provided with external connection terminals
32
comprised of wires bent into L-shapes.
In the examples shown in the above
FIGS. 12A
to
12
I and
FIGS. 13A
to
13
I, the conductive layer
16
was formed on the passivation film
14
, but it is also possible to cover the passivation film
14
by a polyimide film and form the conductive layer
16
on the surface of the polyimide film.
Steps for producing a semiconductor device using the above copper posts as external connection terminals and steps for producing a semiconductor device using gold wires bent into L-shapes as external connection terminals are shown in
FIGS. 14 and 15
. The steps produce chip-sized semiconductor devices by processing the semiconductor wafer to form external connection terminals electrically connected to the electrode terminals formed on it, then dicing the semiconductor wafer. In this way, the methods of the prior art utilize complicated steps, so there are the problems that the production efficiency is reduced and the manufacturing costs increased.
Further, there have been the following problems when mounting a semiconductor device produced by a method of production of the prior art to a board: When mounting a semiconductor device using copper posts as external connection terminals by solder, the solder does not form meniscuses and the external connection terminals are not reliably bonded with the board. When mounting a semiconductor device provided with external connection terminals formed by bending gold wires in L-shapes, due in part to the fact that the heights of the external connection terminals are about 700 to 800 &mgr;m, the semiconductor device and the board are bonded spaced away from each other.
SUMMARY OF THE INVENTION
The present invention was made to solve the problems in the methods of production of the prior art for producing semiconductor devices by processing a semiconductor wafer. An object of the present invention is to provide a highly reliable semiconductor device able to be produced by a simpler method and thereby able to improve the production efficiency and able to arrange external connection terminals at a higher density and thereby able to handle a greater number of pins and a method of production of the same.
To attain the above object, according to a first aspect of the present invention, there is provided a semiconductor device provided with semiconductor elements, such as transistors, formed on a semiconductor substrate, external connection terminals connecting these elements to an external circuit, and interconnection patterns connecting electrodes of the semiconductor elements to the external connection terminals, wherein the external connection terminals are formed by wires comprised of a conductive material and the parts of the wires bonded to the interconnection patterns are buried in the metal layer forming the interconnection patterns.
The metal layer forming the interconnection patterns is preferably formed by copper plating, gold plating or
Paul & Paul
Potter Roy
Shinko Electric Industries Co. Ltd.
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