Semiconductor device and method of production of same

Details Semiconductor device and method of production of same Semiconductor device and method of production of same

2001-10-09

2003-03-25

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S774000, C257S775000, C257S792000

Reexamination Certificate

active

06538332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with a plurality of semiconductor chips and a method for production of the same. More particularly, it relates to a technique useful for reducing the size of a semiconductor device provided with a plurality of semiconductor chips and reducing the cost of the method of production of a semiconductor device.
2. Description of the Related Art
In recent years, the reduction in size of electronic apparatuses has led to a demand for a reduction in size of the semiconductor devices mounted in such electronic apparatuses. Giving one example, a semiconductor device provided with a plurality of semiconductor memory chips has been demanded to increase the storage capacity in a limited mounting region. Such a semiconductor device of the related art will be explained first with reference to FIG.
8
.
FIG. 8
is a sectional view of a semiconductor device of the related art.
The semiconductor device
101
shown in
FIG. 8
is comprised of two semiconductor devices
108
each comprised of a semiconductor chip
106
flip-chip bonded to an interconnection substrate
109
stacked above and below each other. The interconnection substrate
109
is comprised of a polyimide film
102
and interconnection pattern
103
. Among these, the polyimide film
102
is formed with through holes
102
a
,
102
a
, . . . . Further,
107
,
107
, . . . are solder bumps. These are electrically connected with the above interconnection pattern
103
through the through holes
102
a
,
102
a
, . . . . Note that the interconnection pattern
103
is comprised of copper.
Looking at the semiconductor chip
106
, stud bumps
105
,
105
, . . . comprised of gold are formed on its electrode terminal forming surface. These stud bumps
105
,
105
, . . . are electrode terminals of the semiconductor chip
106
and are electrically connected with the interconnection pattern
103
through an anisotropic conductive film
104
.
As illustrated, the solder bumps
107
,
107
, . . . of the upper semiconductor device
108
are bonded on to the interconnection pattern
103
of the lower semiconductor device
108
. Due to this, the upper and lower semiconductor devices
108
are electrically and mechanically connected. Further, by reflow of the solder bumps
107
,
107
, . . . of the lower semiconductor device
108
in the state with the solder bumps
107
,
107
, . . . abutting against the mounting board
110
, the semiconductor device
101
and the mounting board
110
are electrically and mechanically connected. Further, the thickness of the lower and upper semiconductor devices
108
is about 300 &mgr;m, while the overall thickness of the semiconductor device
101
is about 600 &mgr;m.
According to the semiconductor device
101
, since two semiconductor chips
106
are provided in the thickness direction, it is possible to reduce the mounting area compared with when arranging two semiconductor chips
106
in one plane.
Next, an explanation will be made of the method of production of this semiconductor device
101
of the related art while referring to
FIGS. 9A
to
9
N.
FIGS. 9A
to
9
N are sectional views of the method of production of a semiconductor device according to the related art.
First, to produce the upper semiconductor device
108
, as shown in
FIG. 9A
, a long polyimide film
102
on which a copper foil
111
is bonded is provided.
Next, as shown in
FIG. 9B
, a photoresist
112
is coated on the copper foil
111
.
Next, as shown in
FIG. 9C
, an interconnection pattern is exposed on the photoresist
112
. In the figure,
112
a
shows a photoresist sensitized by this exposure.
Next, as shown in
FIG. 9D
, the photoresist
112
is developed. Due to this, only the exposed photoresist
112
a
remains on the copper foil
111
. The surface of the copper foil
111
at the portions not becoming interconnections is exposed.
Next, as shown in
FIG. 9E
, the portions of the copper foil
111
with exposed surfaces are etched. Due to this step, the parts of the copper foil
111
at the portions not becoming interconnections are removed and an interconnection pattern
103
(see
FIG. 8
) is formed on the polyimide film
102
.
Next, as shown in
FIG. 9F
, the interconnection pattern
103
is made to face vertically downward and the sensitized photoresist
112
a
is removed.
Next, as shown in
FIG. 9G
, a laser beam is focused on the polyimide film
102
to form the through holes
102
a
,
102
a
, . . . (see FIG.
8
). Due to the steps up to here, an interconnection substrate
109
comprised of the polyimide film
102
and the interconnection pattern
103
is completed.
Next, as shown in
FIG. 9I
, a film-like anisotropic conductive film
104
is bonded to the interconnection pattern
103
.
Next, as shown in
FIG. 9J
, a semiconductor chip
106
is placed on the anisotropic conductive film
104
. At this stage, the semiconductor device
106
is placed on the anisotropic conductive film by an extremely weak force. Sufficient bonding force between the semiconductor chip
106
and the interconnection substrate
109
is not yet obtained. Further, sufficient electrical connection between the stud bumps
105
,
105
. . . and interconnection pattern
103
is not yet obtained either.
Next, as shown in
FIG. 9K
, the interconnection substrate
109
is placed on a stage
113
where a tool
114
is pressed against the semiconductor chip
106
and the anisotropic conductive film
104
is heated. Due to this, the anisotropic conductive film
104
is heated and pressed to cure, whereby a sufficient bonding force is obtained between the interconnection substrate
109
and the semiconductor chip
106
. Further, due to the pressure, the portions of the anisotropic conductive film
104
sandwiched between the stud bumps
105
,
105
, . . . and the interconnection pattern
103
are given conductivity, whereby the semiconductor chip
106
and the interconnection substrate are electrically connected. Below, the step of heating and pressing the anisotropic conductive film in this way will be called the “main press bonding step”.
When this main press bonding step is finished, the step shown in
FIG. 9L
is performed. In this step, solder bumps
107
,
107
, . . . are placed on the parts of the interconnection pattern
103
exposed from the through holes
102
a
,
102
a . . . .
In the above figures, the portion corresponding to a single semiconductor device
108
is shown, but in practice, as shown in
FIG. 9M
, a plurality of semiconductor devices
108
are formed on a long polyimide film
102
.
Next, as shown in
FIG. 9N
, the polyimide film
102
is cut to separate the plurality of semiconductor devices
108
into individual pieces.
Finally, each of the individual pieces of the semiconductor devices
108
is inspected to determine if it satisfies predetermined specifications for electrical characteristics.
Due to this, the upper semiconductor device
108
shown in
FIG. 8
is completed.
The main points of the above production process may be summarized as in FIG.
10
.
FIG. 10
is a flow chart of the main points of the method of production of a semiconductor device of the related art.
As shown at the left in
FIG. 10
, the production process of the upper semiconductor device
108
is comprised of the following six steps:
Step P
1
: Bonding of anisotropic conductive film
104
(step of
FIG. 9I
)
Step P
2
: Mounting of semiconductor chip
106
(step of
FIG. 9J
)
Step P
3
: Main press bonding (step of
FIG. 9K
)
Step P
4
: Mounting of solder bumps
107
(step of
FIG. 9L
)
Step P
5
: Separation into individual-pieces (step of
FIG. 9N
)
Step P
6
: Inspection
Further, the lower semiconductor device
108
(see FIG.
8
), as shown at the right side of
FIG. 10
, is produced by the same six steps as the production process of the upper semiconductor device
108
. When the lower semiconductor device
108
is completed, it is stacked together with the already completed upper semiconductor device
108
to complete the semiconductor device
1

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