Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-06-14
2005-06-14
Tran, Thien F (Department: 2811)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S426000, C438S427000
Reexamination Certificate
active
06905942
ABSTRACT:
In a semiconductor device having element isolation made of a trench-type isolating oxide film13, large and small dummy patterns11of two types, being an active region of a dummy, are located in an isolating region10, the large dummy patterns11bare arranged at a position apart from actual patterns9, and the small dummy patterns11aare regularly arranged in a gap at around a periphery of the actual patterns9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film13ais improved, and surface flatness of the semiconductor device becomes preferable.
REFERENCES:
patent: 5902752 (1999-05-01), Sun et al.
patent: 5911110 (1999-06-01), Yu
patent: 5976949 (1999-11-01), Chen
patent: 6281049 (2001-08-01), Lee
patent: 10-92921 (1998-04-01), None
patent: 1998-050146 (1998-09-01), None
McDermott Will & Emery LLP
Renesas Technology Corp.
Tran Thien F
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