Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-10-11
2003-02-18
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S513000
Reexamination Certificate
active
06521969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, in particular, an isolating oxide film in a semiconductor integrated circuit device and a pattern of an electrical active region surrounded by the isolating oxide film.
2. Discussion of Background
In recent years, in accordance with micro miniaturization and high-integration of elements of semiconductor integrated circuit devices, design rules become further specific, and a process becomes very complicated. Especially, in an element isolation, a trench-type isolating oxide film, suitable for micro miniaturization, is widely used. Therefore, it is very important to properly embed the isolating oxide film in a trench without spoiling a performance of an electrical active device region and to polish by a CMP method with high reliability.
FIG. 9
is a plan view of a conventional semiconductor device in which elements are isolated. As illustrated in
FIG. 9
, a pattern
1
of an electrical active device region, in which elements are formed, is arranged so as to be surrounded by an isolating region
2
. Particularly, numerical reference la designates a micro width pattern in the electrical active device region, hereinbelow the micro width pattern is referred to as an actual micro pattern
1
a.
FIGS. 10
a
and
10
b
are cross-sectional views of the conventional semiconductor device illustrated in
FIG. 9
, in which semiconductor device the elements are isolated.
FIG. 10
a
is the cross-sectional view taken along a line A
9
—A
9
in
FIG. 9
, in which the isolating region
2
, being relatively wide, is shown.
FIG. 10
b
is the cross-sectional view taken along a line B
9
—B
9
in
FIG. 9
, wherein the actual micro pattern
1
a,
which is surrounded by the isolating regions
2
on both of sides, is shown.
An element isolation in a semiconductor device is formed by sequentially arranging an underlayer oxide film
4
and a nitride film
5
on a semiconductor substrate
3
.
Thereafter, after selectively etching to remove a part of the nitride film
5
, to be the isolating region
2
, the semiconductor substrate
3
is etched using a mask of the nitride film
5
, whereby a trench having a predetermined depth is formed. Succeedingly, after forming an isolating oxide film
7
on an entire surface of the semiconductor substrate
3
so as to fill an inside of the trench
6
, the isolating oxide film
7
is abraded by a CMP method to remove the isolating oxide film
7
on the nitride film
5
and leave the isolating oxide film
7
only inside the trench
6
, whereby a trench-type isolating oxide film
7
a
is formed. The nitride film
5
and the underlayer oxide film
4
are removed after forming the element isolation.
However, the conventional semiconductor device has a problem that an abrading rate is decreased at around a region where the nitride film
5
is formed by an influence of the nitride film
5
because the isolating oxide film
7
on the nitride film
5
is removed by abrasion using a CMP method, the abrading rate of the nitride film
5
is low. On the contrary, in the wide isolating region
2
, i.e. the trench-type isolating oxide film
7
a,
illustrated in
FIG. 10
a,
the abrading rate is high, and a sink is produced in a film in its thickness direction by dishing especially in a central portion. Therefore, there are problems that a flatness of a surface is deteriorated, and a later process of patterning using a lithography technique is inappropriately patterned.
Further, as illustrated in
FIG. 10
b,
when the actual micro pattern
1
a
is surrounded by the wide isolating regions
2
, i.e. the trench-type isolating oxide films
7
a,
there is a case that a part or all of the nitride film
5
of the actual micro pattern
1
a
is abraded by overpolishing as illustrated in
FIG. 11
because an abrading rate for the trench-type isolating oxide films
7
a
is high. Therefore, there are problems that the film thicknesses of the trench-type isolating oxide films
7
a
have further large sinks, and electrical characteristics of element are deteriorated such that a threshold value is deteriorated by an inverse narrow channel effect in properties of transistor and a leakage current is increased.
In order to improve the above-mentioned problems, in a conventional technique, a dummy pattern, being an active region of a dummy, is located in the isolating region
2
to improve uniformity of an abrading rate by a CMP method.
FIGS. 12 and 13
are plan views illustrating examples of improvement of conventional semiconductor devices, in which dummy patterns
8
, i.e. active regions of a dummy, are arranged in the isolating region
2
of the semiconductor device illustrated in FIG.
9
. In
FIG. 12
, relatively small dummy patterns
8
a
are bedded in the isolating region
2
. In
FIG. 13
, relatively large dummy patterns
8
b
are bedded in the isolating region
2
.
When the isolating oxide film
7
is abraded by the CMP method in a case illustrated in
FIG. 12
, an abrading rate for a region, where the small dummy patterns
8
a
cluster, is lowered. Accordingly, there is a case that the isolating oxide film
7
is left on the nitride film
5
of the dummy pattern
8
a
by under-polishing as illustrated in a cross-sectional view of FIG.
14
. In this case, not only the isolating oxide film
7
but also the nitride film
5
and an underlayer oxide film
4
, which are located on a lower side of the isolating oxide film
7
, are not removed by a 'succeeding removing step, whereby flatness of a surface is extremely spoiled, and it becomes difficult to pattern in a later step.
Further, in the case illustrated in
FIG. 13
, because the dummy patterns
8
b
are large, there are areas where the dummy patterns are not arranged in a periphery of the actual pattern
1
. Especially, when the dummy patterns
8
b
do not exist in the periphery of the actual micro pattern
1
a,
a cross-sectional view taken along a line B
13
—B
13
is similar to that in
FIG. 10
b.
As illustrated in
FIG. 11
, because of the high abrading rate or the trench-type isolating oxide films
7
a,
there is a case that a part or all of the nitride film
5
of the actual micro pattern
1
a
is abraded by over-polishing. Therefore, as described above, the sinks in the trench-type isolating oxide films
7
a
become further large, whereby electrical characteristics of element are deteriorated.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the above-mentioned problems inherent in the conventional technique and to provide a semiconductor device with an element isolation, made of a trench-type isolating oxide film formed in an isolating region, wherein overpolishing and under-polishing are restricted by improving uniformity of an abrading rate at time of abrading the isolating oxide film by a CMP method, whereby the semiconductor device has a preferable surface flatness and high reliability.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate;
electrical active device regions formed in the semiconductor substrate; and
an isolating region made of a trench-type isolating oxide film, of which surface is abraded by a CMP method,
wherein a plurality of types of dummy patterns having various areas, being active regions of a dummy surrounded by the trench-type isolating oxide film patterns, are located in the isolating region so that the trench-type isolating oxide film pattern does not exceed a predetermined width, and
the dummy patterns are regularly arranged by setting an area in response to a positional relationship between the dummy patterns and patterns of the electrical active device regions.
According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect of the invention,
wherein relatively large dummy patterns are arranged from a position apart from the electrical active device patterns to the electrical active device patterns, and
relatively small d
Mitsubishi Denki & Kabushiki Kaisha
Thomas Tom
Tran Thien F
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