Radiation imagery chemistry: process – composition – or product th – Plural exposure steps
Reexamination Certificate
2000-04-05
2003-12-09
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Plural exposure steps
C430S005000, C430S313000, C430S330000, C430S396000
Reexamination Certificate
active
06660462
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device including a logic semiconductor integrated circuit such as a CMOS logic LSI and a method of producing the semiconductor device.
Improvement in circuit performance and increase in integration density of a semiconductor integrated circuit (LSI) have been achieved by making a circuit pattern finer. In particular, in a logic LSI, its operating speed (operating frequency) has been improved by shortening a transistor gate length (Lg).
In formation of the circuits, photolithography (reduction projection exposure method) is used at present. The resolution has been improved by shortening the exposure wavelength and increasing numerical aperture of projection optics.
At present, the transistor gate length Lg has been shortened to 0.18 micron by using a KrF excimer laser exposure apparatus (wavelength of 248 nm). The intervals (pitches) of gates and wires have been being reduced to improve the integration density. It is presumed that 0.5 micron or less can be realized by using the KrF exposure apparatus.
It is expected that by using an ArF excimer laser exposure apparatus (wavelength of 193 nm), each of the transistor gate length Lg and the pitch can be reduced further by about 20 percent, but it is difficult to realize further reduction by a conventional reduction projection exposure method using deep ultra-violet radiation.
On the other hand, in photolithography, as a method of improving resolution without changing optics, a phase shifting mask is known. According to the method, by controlling (usually, inverting) the phase of light passing through a specific aperture in the mask, the resolution of the optics is improved much more than the case of using a conventional mask.
Among various kinds of phase shifting masks, an alternating phase shifting mask produces the highest effect on improvement in resolution.
The phase shifting method is described in, for example, “ULSI Lithography Technical Renovation”, SCIENCE FORUM TOKYO, pp. 34-40, 1994.
Although the alternating phase shifting method is easily applied to alternating patterns as the name implies, generally, it cannot be always applied to a pattern of an arbitrary shape. For example, it is difficult to dispose a shifter in the case of a U-letter shaped pattern or three aperture patterns arranged at the shortest distance.
A method of performing multiple-exposure onto the same resist film by using a plurality of masks including the phase shifting mask to enable an arbitrary-shaped pattern to be transferred has been applied by the inventors of the present invention in Japanese Patent Nos. 2650962 (Publication of Japanese Unexamined Patent Application No. 1-283925) and 2638561 (Publication of Japanese Unexamined Patent Application No. 8-51068). The method is applied to, for example, a process of forming a gate of a logic LSI which has to be formed by controlling the line width of an extremely thin line pattern with high accuracy. Specifically, by disposing a phase shifter (region in which the phase of transmission light is inverted on a mask) so that the phases in the apertures on both sides of a gate are inverted, the resolution, line width accuracy, depth of focus, and the like of a transistor gate pattern can be largely improved.
Since an edge portion of the phase shifter is, however, generally transferred as an unnecessary pattern, in order to prevent it, it is necessary to divide an original design pattern into two mask patterns and perform multiple exposure.
For example, multiple exposure is performed on the same positive resist film by using two masks of a first mask
1
A as shown in
FIGS. 1A-1B
and a second mask
1
B as shown in FIG.
1
C and developed. The first mask
1
A has apertures
1
a
and
1
b
on both sides of a part (indicated as a region a) corresponding to a fine gate in an active region. A phase shifter
2
is provided for one of the apertures, for example
1
a
, so that the phases of light passing the apertures
1
a
and
1
b
neighboring the region (a) corresponding to the gate are opposite to each other. The second mask
1
B includes a light shielding pattern
3
for covering the gate (region a) and a light shielding pattern
4
formed in the same layer as the light shielding pattern
3
, for covering the region other than the fine gate.
Consequently, as shown in
FIG. 1D
, a desired resist pattern
5
is formed on a wafer. Narrow portions of the resist pattern
5
correspond to the gate mask formed by the light shielding pattern
3
of the second mask
1
B. Similarly, thick portions correspond to the mask which is, for example, a wiring pattern formed by the light shielding pattern
4
of the second mask
1
B.
The patterns on the two masks can be automatically generated from the original design pattern by a geometrical operation and a dedicated program for automatically generating patterns has been also developed.
It is considered that by using the method, the transistor gate length Lg can be reduced to about 0.12 micron by employing a KrF exposure apparatus. The combination of the masks to form the resist pattern of
FIG. 1D
is not limited to that of the masks
1
A and
1
B. For example, in place of the mask
1
B, a mask
1
D in which light shielding portions on fine gates are broadened as shown in
FIG. 1E
can be used.
The improvement in accuracy of the dimension is as important as the reduction in the transistor gate length Lg. The required dimensional accuracy of the a transistor gate length Lg is about 10% of normal design dimension. When the KrF exposure apparatus is used, it is therefore necessary to perform a dimension control at a 10 nm level. One of factors of deterioration in dimensional accuracy is a proximity effect such that the dimension and shape of a pattern fluctuate due to an influence of adjacent patterns.
Specifically, when transistor gate patterns (narrow portions) having uniform length Lg variously disposed as design mask patterns as shown in (a) of
FIG. 2A
are transferred onto a wafer, as shown in (b), the dimensions of actually etched gate patterns change according to the disposing state of the designed patterns. That is, as shown in the diagram, the designed gate pattern (narrow portion) becomes thick as a whole or partially.
It is known that the phenomenon is caused by complicatedly connected various effects such as a pure optical effect by diffraction of light, diffusion of reaction products in the resist, dependence on a developed area of a development rate, and a (micro)loading effect at the time of etching.
In order to solve the problem, therefore, an optical proximity effect correction technique for correcting the dimension of a mask pattern in consideration of the proximity effect has been being examined. To be specific, as schematically showing a correction mask in (c) of
FIG. 2B
, by correcting the design dimension of the transistor gate length Lg on the mask, the dimension of the gate pattern actually obtained on a wafer can be uniformized as shown by (d) in FIG.
2
.
The correction of the light proximity effect is described in, for example, Proceedings of SPIE, Vol. 3334, pp. 921-931, 1998.
The proximity effect correction has, however, a problem such that very long time is required for a correction since a pattern is designed by estimating the degree of the proximity effect. Particularly, in the case of using a phase edge, a problem such that a correction rule is complicated. Further, exposure characteristics largely vary according to a distance to an adjacent gate. Especially, since the manner of a change in line width in association with deforcusing (hereinbelow, called defocus characteristics) largely varies, the following problem arises. Even if the proximity effect is corrected under certain optimum focusing conditions, when defocusing occurs on an actual wafer, the effect of the correction is lost.
Focus characteristics for the same design dimension patterns disposed at different pitches draw, for example, tw
Chacko-Davis Daborah
Hitachi , Ltd.
Huff Mark F.
Mattingly Stanger & Malur, P.C.
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