Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1999-09-20
2003-03-25
Lee, Eddie (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S051000, C257S066000, C257S347000
Reexamination Certificate
active
06538268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same, more specifically this invention relates to a semiconductor device to effectively prevent the body floating effect and various related problems in MOS field effect transistors formed on a SOI (silicon-on-insulator) substrate, and a method for easily producing the semiconductor device.
2. Description of Related Art
A semiconductor device having various elements such as transistors formed on a single crystalline silicon layer formed on an insulator is known as a structure called SOI (Silicon On Insulator). The structure shown in
FIG. 2
for example is disclosed on page 755 of the Extended Abstracts (the Spring Meeting, 1995) The Japan Society of Applied Physics and Related Societies. The MOS field effect transistor (hereafter simply referred to as MOS) is formed on a single crystalline silicon (Si) layer
3
separated from a handle wafer
1
by a thick insulator
2
. The reference numeral
4
in
FIG. 2
indicates a device isolation layer, the numeral
5
indicates a gate insulator, the numeral
6
is a gate electrode, the numeral
7
is a gate electrode protection insulator, the numeral
8
is a gate side-wall insulator, the numerals
9
and
10
are n-type highly concentrated impurity diffusion regions with respective drain and source regions.
The special feature of SOI-MOS of the conventional art as shown in
FIG. 2
, is that a thick device insulation layer
2
, is present directly beneath the single-crystalline silicon (Si) layer
3
so that the parasitic wiring capacitance and the drain junction capacitance are reduced to approximately one-tenth of the capacitance of an ordinary MOS formed on an Si substrate. Another feature is that the MOS is also isolated by insulation from the handle wafer
1
so that misoperation due to alpha ray beam irradiation and latch-up phenomenon are essentially eliminated.
However, in an SOI-MOS device of this type, the single crystalline silicon (Si) layer
3
is completely isolated from the handle wafer
1
so that minority carriers (holes) generated for example, by the strong electrical field of the drain tend to transiently accumulate within the single crystalline silicon (Si) layer
3
and cause a shifting threshold voltage or so-called body floating effect. This body floating effect can be viewed as the parasitic bipolar effect that causes majority carriers to flow in as a result of a rise in electrical potential due to accumulation of minority carriers within the single crystalline silicon (Si) layer
3
. In n-channel SOI-MOS devices, (hereafter abbreviated to n-SOI-MOS) the threshold voltage fluctuates in the negative direction due to the accumulated holes and an abnormal bump can be observed in the device current/voltage characteristics (kink characteristic). This condition causes problems such as a large leakage current when the device is in the off state and a lowering the source and drain breakdown voltage which can be a fatal defect in differential amplifiers and analog circuits which must detect tiny differences in the electrical current.
In the SOI-MOS device shown in
FIG. 2
, in order to prevent the above mentioned body floating effect, germanium (Ge) is ion-implanted into a source highly-concentrated impurity diffusion region
9
and a SiGe alloy
14
with a Ge content of approximately 10 percent is formed.
FIG. 3
shows the energy band diagram along the channel when a voltage is applied to the drain of the SOI-MOS device in FIG.
2
. In
FIG. 3
, E
Fn
is the pseudo-fermi level and E
i
is the intrinsic fermi level. The bandgap narrows by approximately 0.1 eV by forming the SiGe alloy
14
, the valence band E
v
for the source is formed as shown by the broken line, and the difference in hole diffusion potential is reduced. As a result, the holes generated near the drain and accumulating within the single crystalline silicon (Si) layer
3
tend to diffuse within the source and be eliminated. The conduction band E
c
is unaffected by the SiGe alloy
14
and there are no adverse effects on the behavior of electrons which are majority carriers.
However, due to control of the valence band at the source junction the structure shown in
FIG. 2
is inadequate for eliminating the body floating effect in p-channel SOI-MOS devices (hereafter abbreviated to pSOI-MOS), and when germanium (Ge) is introduced into the source region of the pSOI-MOS device, the difference in diffusion potential drops and the breakdown voltage deteriorates. Further, in nSOI-MOS devices since the body floating effect cannot be adequately eliminated, and an excessive amount of germanium (Ge) of more than 10 percent is injected into the source region, the problem of crystalline defects occurs due to the difference in lattice constants of the Si (silicon) and Ge (germanium). The only way to eliminate the crystalline defects is to reduce the Ge (germanium) content however, the improved drop in diffusion potential does not amount to more than approximately 0.1 eV which is inadequate to eliminate the body floating effect.
The SOI-MOS device of
FIG. 4
is disclosed on page 627 of the Extended Abstracts of the 1995 International Electron Devices Meeting and the SOI-MOS device of
FIG. 5
is disclosed on page 337 of the Extended Abstracts of the 1992 International Electron Devices Meeting.
In the SOI-MOS device of
FIG. 4
, after forming the source and drain diffusion regions
9
and
10
, argon (Ar) is ion-implanted and a recombination center region
15
formed within the source and drain, and the holes that accumulated inside the single-crystalline silicon (Si) layer
3
are eliminated. However, unless the position of the recombination center region
15
versus the drain junction is optimal, then the leakage current tends to increase so that also eliminating the holes within the single-crystalline silicon (Si) layer
3
is extremely difficult.
In the SOI-MOS device of
FIG. 5
however, a portion of the junction of the bottom of the source
9
is destroyed by a spike
16
resulting from abnormal diffusion of a metal electrode and the holes within the single-crystalline silicon (Si) layer
3
are eliminated by this spike
16
. In this structure, in order to maintain a flow path for the positive holes, from the single-crystalline silicon (Si) layer
3
, a portion below the bottom of the source
9
is used as the P-type highly concentrated impurity region, and a portion below the drain
10
is used as an N-type highly concentrated impurity region to prevent the spike
16
from causing a deterioration in the transistor characteristics. As a result, the source
9
and the drain
10
are not symmetrical and the device is not usable in general purpose.
SUMMARY OF THE INVENTION
Accordingly it is an object of the present invention to resolve the above mentioned problems with the SOI-MOS device of the conventional art in
FIG. 2
, by providing an SOI-MOS device having a new structure and a production method for this device, applicable even to p-SOI-MOS devices as well as complementary SOI-MOS devices and further capable of preventing crystalline defects in the active region and the body floating effect.
It is a further object of the present invention to resolve the above mentioned problems with the SOI-MOS device of the conventional art in
FIG. 4
, by providing an SOI-MOS device having a new structure and a production method for this device, to stop the occurrence of defects in the active regions of the source and drain and also adequately prevent the body floating effect.
A yet further object of the present invention is to resolve the above mentioned problems with the SOI-MOS device of the conventional art in
FIG. 5
, by providing an SOI-MOS device having a new structure and a production method for this device, that is widely applicable to semiconductor integrated circuits having a symmetrical structure of source and drain, and also prevents the body floating effect.
A still further object of the present invention is to provide a
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lee Eddie
Pizarro-Crespo Marcos D.
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