Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2007-07-03
2007-07-03
Schillinger, Laura M. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S209000, C257S315000
Reexamination Certificate
active
10978216
ABSTRACT:
A semiconductor device comprises a memory cell (160) including a transistor body (150) having a top surface (111) and including a first doping area (10a) and a second doping area (10b) with a channel region (110) in between. The memory cell (160) further includes a gate electrode (3a) arranged above the channel region (110) and separated therefrom by a dielectric layer (2a). An oxide-nitride-oxide layer (66) has first portions (661) and second portions (662). The first portions (661) of the oxide-nitride-oxide layer (66) are arranged above at least parts of the first and second doping areas (10a, 10b) and are substantially parallel to the top surface (111) of the transistor body (150). The second portions (662) of the oxide-nitride-oxide layer (66) are adjacent to the gate electrode (3a) and extend in a direction not substantially parallel to the top surface (111) of the transistor body (150).
REFERENCES:
patent: 6011725 (2000-01-01), Eitan
patent: 6358864 (2002-03-01), Chang et al.
patent: 6498084 (2002-12-01), Bergemont
patent: 6642586 (2003-11-01), Takahashi
patent: 6740605 (2004-05-01), Shiraiwa et al.
patent: 6756271 (2004-06-01), Satoh et al.
patent: 6927133 (2005-08-01), Takahashi
patent: 6962842 (2005-11-01), Kalnitsky et al.
patent: 2002/0168843 (2002-11-01), Bergemont
patent: 2003/0219944 (2003-11-01), Kato et al.
patent: 2003/0235952 (2003-12-01), Shibata
patent: 2004/0028733 (2004-02-01), Tomiie et al.
patent: 2004/0048433 (2004-03-01), Takahashi
patent: 2006/0091424 (2006-05-01), Strassburg et al.
patent: 2006/0131672 (2006-06-01), Wang et al.
patent: 1 231 646 (2002-08-01), None
patent: 1231646 (2002-08-01), None
patent: WO 01/17030 (2001-03-01), None
Eitan, B., et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, Nov. 2000, pp. 543-545, vol. 21, No. 11.
Kang, S.T., et al., “A Study of SONOS Nonvolatile Memory Cell Controlled Structurally by Localizing Charge-Trapping Layer,” Proc. IEEE Non-Volatile Memory Workshop, Monterey, 2003, pp. 39-41.
Shappir, J., et al., “Split Nitride NROM in 0.09u Generation,” Aug. 12, 2002, Saifun Semiconductors Ltd., 14 Seiten, pp. 1-14.
Tsai, W.J., et al., “Novel PHINES Flash EEPROM with 0.046um2Bit Size for Giga-bit Era Application,” Technology Development Center, Macronix International Co., Ltd, (4 pages).
Riedel Stephan
Strassburg Matthias
Infineon - Technologies AG
Schillinger Laura M.
Slater & Matsil L.L.P.
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