Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – With doping profile to adjust barrier height
Reexamination Certificate
1997-12-10
2002-12-31
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
With doping profile to adjust barrier height
C257S471000, C257S283000, C257S622000
Reexamination Certificate
active
06501146
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. The invention particularly relates to a semiconductor device which has a higher withstand voltage and in which the reverse recovery current is reduced, and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
A semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) is applied to various inverter circuits as a switching element. In order to release the energy stored in an inductive load in the switching process and utilize it as the circulating current, a diode is connected in antiparallel with a main semiconductor device. Such a diode is especially referred to as a flywheel diode.
Excess carriers are stored in a diode in the forward bias state, that is, in the ON state. The stored excess carriers are released in the process of transition to the OFF state, that is, the reverse bias state. At this time, current flows in a direction opposite to the forward direction of the diode. This current is especially referred to as reverse recovery current which flows into a semiconductor device such as the IGBT, resulting in the loss. The excess carriers which constitute the reverse recovery current are, in this case, minority carriers or holes.
A diode in which the minority carriers are not stored is the Schottky diode. Description of the Schottky diode is given below referring to the figure. With reference to
FIG. 54
, at one surface of an n
−
substrate
101
, a silicon oxide film
107
is formed. An anode metallic electrode
105
is further formed via a Schottky junction region
104
. At the other surface of n
−
substrate
101
, a cathode metallic electrode
106
is formed via an n
+
cathode region
102
.
In this structure, most current flowing through Schottky junction region
104
is constituted by the majority carriers. Therefore, no minority carrier is stored in n
−
substrate
101
, and the reverse recovery current is small. As a result, a high speed switching is possible. However, the withstand voltage in the reverse bias state depends on Schottky junction region
104
. The withstand voltage is about 100V at most, and improvement of the withstand voltage is impossible.
In order to improve the withstand voltage, a structure has been used in which a pn junction is provided around the Schottky junction region, a depletion layer extending from the pn junction in the reverse bias state is utilized, and the withstand voltage is obtained. A first conventional diode having such a structure is described referring to the figure. With reference to
FIG. 55
, a plurality of p anode regions
103
are formed at one surface of n
−
substrate
101
. On the one surface of n
−
substrate
101
including p anode regions
103
, an anode metallic electrode
105
is formed. Schottky junction region
104
is formed between anode metallic electrode
105
and n substrate
101
. On the other surface of n
−
substrate
101
, a cathode metallic electrode
106
is formed via n
+
cathode region
102
.
In this diode, a depletion layer extends from an interface between p anode regions
103
and n
−
substrate
101
toward the n
−
substrate particularly in the reverse bias state. In the vicinity of Schottky junction region
104
, the depletion layers extending from the interfaces between the adjacent p anode regions
103
and n
−
substrate
101
connect with each other, easing the electric field. As a result, the withstand voltage in the reverse bias state is improved compared with the Schottky diode.
A second conventional diode is described referring to the figure. With reference to
FIG. 56
, a plurality of p anode regions
103
are formed at one surface of n
−
substrate
101
. At regions between respective p anode regions
103
, a p
−
region
108
is formed. On p anode regions
103
and p
−
region
108
, anode metallic electrode
105
is provided. On the other surface of the n
−
substrate, cathode metallic electrode
106
is formed via n
+
cathode region
102
.
In this diode, a depletion layer extends from an interface between p anode region
103
and n
−
substrate
101
toward n
−
substrate
101
, and a depletion layer further extends from an interface between p
−
region
108
and n
−
substrate
101
toward n
−
substrate
101
, particularly in the reverse bias state. As a result, the withstand voltage is further improved compared with the diode shown in FIG.
55
.
A third conventional diode disclosed in Japanese Patent Laying-Open No. 4-321274 is described referring to the figure. With reference to
FIG. 57
, a plurality of concave portions
206
are formed at one surface of a semiconductor substrate of one conductivity type
201
. A semiconductor region of opposite conductivity type
204
is formed along an inner surface of each concave portion
206
. A one electrode metal
205
is formed on one conductivity type semiconductor substrate
201
including the surface of concave portion
206
. On the opposite side of one conductivity type semiconductor substrate
201
, an ohmic electrode metal
203
is formed via a one conductivity type semiconductor
202
of low resistance. One conductivity type semiconductor substrate
201
and one electrode metal
205
constitute the Schottky barrier junction.
In this diode, a depletion layer extends from an interface between semiconductor region of opposite conductivity type
204
and semiconductor substrate of one conductivity type
201
toward one conductivity type semiconductor substrate
201
in the reverse bias state. At this time, the portion adjacent to the interface between one conductivity type semiconductor substrate
201
and one electrode metal
205
is sandwiched between the depletion layers. Accordingly, in a portion adjacent to one conductivity type semiconductor substrate
201
and one electrode metal
205
, the electric field is eased and the withstand voltage is improved.
Next a fourth conventional diode disclosed in U.S. Pat. No. 4,982,260 is described. Referring to
FIG. 58
, on one surface of a first semiconductor substrate layer
502
, a second semiconductor layer
506
is formed. At a main surface
508
of the second semiconductor layer
506
, a plurality of trenches
512
A-
12
F are formed. P
+
regions
510
A-
10
D as well as mesa regions
514
A-
14
C are alternately provided between adjacent trenches. The depth of p
+
regions
510
A-
10
D is substantially identical to that of trenches
512
A-
12
F. Oxide layers
522
A-
22
F are respectively formed at respective inner surfaces of trenches
512
A-
12
F. A metallic anode
518
is formed on main surface
508
of the second semiconductor layer
506
. Schottky barrier regions
550
A-
50
C are formed between metallic anode
518
and the second semiconductor layer
506
. A cathode
504
is formed on the other surface of the first semiconductor substrate layer
502
.
In this diode, a depletion layer extends from an interface between p
+
regions
510
A-
10
D and the second semiconductor layer
506
toward the second semiconductor layer
506
in the reverse bias state. The depletion layer extending from each interface is connected with adjacent depletion layers, and the withstand voltage of the diode is improved.
Another diode disclosed in U.S. Pat. No. 4,982,260 is described as a fifth conventional art using the figure. With reference to
FIG. 59
, on one surface of a first semiconductor substrate layer
702
, a second semiconductor layer
706
is formed. A plurality of trenches
710
A-
710
F are provided at a main surface of second semiconductor layer
706
. At the bottoms of respective trenches
710
A-
710
F, p
+
regions
720
A-
720
F are provided. Respective trenches
710
A-
710
F have their side surfaces at which oxide layers
722
A-
722
J are formed. On the main surface of the semiconductor layer
706
, a metallic anode
716
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nadav Ori
Thomas Tom
LandOfFree
Semiconductor device and method of manufacturing thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2957120