Semiconductor device and method of manufacturing thereof

Details Semiconductor device and method of manufacturing thereof Semiconductor device and method of manufacturing thereof

2000-01-21

2001-08-14

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S773000, C438S014000, C438S599000, C438S622000

Reexamination Certificate

active

06274934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having in addition to a normal electronic circuit a spare electronic circuit which is used in the event of failure of the normal electronic circuit and used when the logic design is changed, and relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
A semiconductor device provided with a spare electronic circuit has conventionally been used. When any failure of a normal electronic circuit or any mistake in a logic design of the entire semiconductor device is discovered by inspection, the spare electronic circuit is substituted for the failed normal electronic circuit or added between normal electronic circuits by just changing metal interconnections, only the spare electronic circuit then connected to other normal electronic circuits, so as to improve the yield of the semiconductor device.
A conventionally used semiconductor device having a spare electronic circuit in addition to a normal electronic circuit is hereinafter described in conjunction with
FIGS. 13
to
15
. The conventional semiconductor device having a spare electronic circuit has, for example, an inverter circuit
108
a
and an NAND circuit
109
a
at a semiconductor substrate
101
as normal electronic circuits as shown in
FIGS. 13 and 14
. Between inverter circuit
108
a
and NAND circuit
109
a
at semiconductor substrate
101
, an inverter circuit
108
b
is provided as a spare which is used as a spare electronic circuit for inverter circuit
108
a
or used for changing the logic design of the entire electronic circuit.
Circuit element formation regions
101
a
and
101
b
are formed at inverter circuit
108
a
. Contact plugs
103
are connected to the source/drain regions of element formation regions
101
a
and
101
b
. A gate electrode
102
a
is provided to element formation regions
101
a
and
101
b
to be located between the source/drain regions.
Circuit element formation regions
101
c
and
101
f
are formed at spare inverter circuit
108
b
. Contact plugs
103
are connected to the source/drain regions of element formation regions
101
c
and
101
f
. A Gate electrode
102
b
is provided to element formation regions
101
c
and
101
f
to be located between the source/drain regions.
Circuit element formation regions
101
d
and
101
e
are formed at NAND circuit
109
a
. Contact plugs
103
are connected to the source/drain regions of element formation regions
101
d
and
101
e
. Gate electrodes
102
c
and
102
d
are formed at element formation regions
101
d
and
101
e
to be located between the source/drain regions.
Contact plugs
104
a
,
104
b
,
104
c
and
104
d
are respectively provided at gate electrodes
102
a
,
102
b
,
102
c
and
102
d
for connecting gate electrodes
102
a
,
102
b
,
102
c
and
102
d
with first metal interconnections located in an upper layer. At the upper ends of contact plugs
104
a
,
104
b
,
104
c
and
104
d
, first metal interconnections
105
a
,
105
b
,
105
c
and
105
d
are formed that extend laterally in
FIG. 13
at a substantially constant height from a main surface of the semiconductor substrate. Outside the region where inverter circuit
108
a
, spare inverter circuit
108
b
and NAND circuit
109
a
are formed, a first metal interconnection
105
e
is formed which laterally extends in
FIG. 13
to connect inverter circuit
108
a
with NAND circuit
109
a.
Second metal interconnections
107
a
,
107
b
,
107
c
,
107
d
,
107
e
,
107
f
,
107
g
,
107
h
and
107
i
are formed in a layer which is located at a greater height from the substrate than the layer where the first metal interconnections
105
a
,
105
b
,
105
c
and
105
d
are formed. Plugs
106
a
,
106
d
,
106
e
,
106
f
,
106
g
,
106
h
and
106
i
are formed in order to connect the first metal interconnections
105
a
,
105
b
,
105
c
and
105
d
with the second metal interconnections
107
a
,
107
b
,
107
c
,
107
d
,
107
e
,
107
f
,
107
g
,
107
h
and
107
i
. These first metal interconnections, plugs and second metal interconnections are formed in an insulating film
200
.
In this conventional semiconductor device thus provided with spare inverter circuit
108
b
, if inverter circuit
108
a
as a normal electronic circuit fails or when logic design is corrected by adding spare inverter circuit
108
b
, spare inverter circuit
108
b
can be utilized. When spare inverter circuit
108
b
is employed, limited layers such as the first metal interconnections, the plugs and the second metal interconnections are changed so as to replace inverter circuit
108
a
with spare inverter circuit
108
b
or to add spare inverter circuit
108
b
between inverter circuit
108
a
and NAND circuit
109
a
, and accordingly repair or change in the electronic circuit structure of the semiconductor device is accomplished. This scheme is employed in order to reduce the manufacturing cost of the semiconductor device as well as the turn-around-time in the manufacturing process of the semiconductor device.
In the above-described conventional semiconductor device having the spare electronic circuit, the second metal interconnections
107
a
and
107
b
which are normal electronic circuit interconnections connected to normal electronic circuits pass through the region where spare inverter
108
b
is formed. Therefore, if any defect in the circuit design is detected by inspection, change in arrangement of the interconnections is inevitable as shown in
FIG. 15
in which the second metal interconnections
107
a
and
107
b
, which pass through the region where spare inverter circuit
108
b
is formed and connect normal circuits with each other, are moved to another region so as to use spare inverter circuit
108
b
. Specifically, the second metal interconnection
107
a
is changed to second metal interconnections
107
m
,
107
k
,
107
p
and first metal interconnections
105
k
and
105
m
, and the second metal interconnection
107
b
is changed to second metal interconnections
107
n
,
107
o
and
107
l
and first metal interconnections
105
l
and
105
n
. As a result, the interconnection route is extended by the lengths of the first metal interconnections
105
l
,
105
n
,
105
k
and
105
m
. If the route made up of the first metal interconnections
105
l
,
105
n
,
105
k
and
105
m
is extremely long, there arises a remarkable difference between the lengths of the electronic circuit interconnections connecting the electronic circuits with each other respectively before the change in the interconnections and after that. This difference of the lengths causes a delay in a pulse which travels between electronic circuits. The delay in the pulse between normal electronic circuits then causes lag of response timing between one electronic circuit and another electronic circuit. Accordingly, if any change is made in the interconnections which is accompanied by change in the arrangement of electronic circuit interconnections established in the original design, the change in the interconnections could adversely influence the entire electronic circuit.
Further, if the required change in interconnections is accompanied by a remarkable change in normal electronic circuit interconnection routes, the normal electronic circuit interconnection routes could be located too close to each other as in the region near the second metal interconnections
107
p
and
107
o
. If the electronic circuit interconnections are extremely close to each other, they could exert adverse electrical effects on each other. Therefore, change in the interconnections which could cause closely located electronic circuit interconnection routes should be avoided. Consequently, it is impossible to easily find out changed interconnection routes which do not introduce the closely located electronic circuit interconnection routes, and thus a spare electronic circuit cannot be utilized easily.
According to the metal interconnection design of the current semiconductor integrated circ

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