Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-09-16
2009-11-17
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S653000, C257SE21682, C257SE21546, C257SE21548
Reexamination Certificate
active
07618876
ABSTRACT:
A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.
REFERENCES:
patent: 6309928 (2001-10-01), Sung et al.
patent: 6391781 (2002-05-01), Ozawa et al.
patent: 6479405 (2002-11-01), Lee et al.
patent: 6656817 (2003-12-01), Divakaruni et al.
patent: 2004/0072429 (2004-04-01), Hieda et al.
patent: 2005/0170608 (2005-08-01), Kiyotoshi et al.
patent: 60-124839 (1985-07-01), None
patent: 10-242264 (1998-09-01), None
patent: 10-308442 (1998-11-01), None
patent: 2001-35914 (2001-02-01), None
patent: 3178412 (2001-04-01), None
patent: 2002-208629 (2002-07-01), None
Notification of Reasons for Rejection issued by the Japanese Patent Office on Apr. 8, 2008, for Japanese Patent Application No. 2005-155806, and English-language translation thereof.
Notification of Reasons for Rejection mailed by the Japanese Patent Office on Aug. 5, 2008, in counterpart Japanese Patent Application No. 2005-155806, and English-language translation thereof.
Arisumi Osamu
Hieda Katsuhiko
Kiyotoshi Masahiro
Tsunashima Yoshitaka
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lindsay, Jr. Walter L
Pompey Ron E
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