Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

1995-02-24

1997-11-04

Niebling, John

Fishing, trapping, and vermin destroying

437 44, 437 61, 437 50, H01L 21265

Patent

active

056839219

ABSTRACT:
A MOS transistor consists of a gate insulating film, a gate electrode, a pair of sidewall spacers on the side faces of the gate electrode, lightly doped source/drain regions, and heavily doped source/drain regions, which are located below the sidewall spacers. Between the sidewall spacers and an isolation are formed concave portions. On a silicon substrate in the concave portions are formed insulating films for capacitance reduction. On the insulating films for capacitance reduction are formed withdrawn electrodes. The heavily doped source/drain regions are electrically connected to the withdrawn electrodes between the sidewall spacers and the insulating films for capacitance reduction. Consequently, a pn junction capacitance beneath the source/drain regions is reduced, while the contact area between the source/drain regions and wiring is surely obtained, thereby achieving higher integration of the MOS transistors.

REFERENCES:
patent: 4862232 (1989-08-01), Lee
patent: 5439839 (1995-08-01), Jang
patent: 5480819 (1996-01-01), Huang
patent: 5494838 (1996-02-01), Chang et al.
"IBM Technical Disclosure Bulletin", vol. 24, No. 1A, Jun. 1981, New York, pp. 57-60.
C.K. Lau et al. "A Super Self-Aligned Source/Drain Mosfet", 1987 International Electron Devices Meeting, IEDM, Technical Digest (Cat. No. 87CH2515-5), Washington, D.C., 6-9 Dec., 1987, pp. 358-361.

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