Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2009-06-02
2010-10-19
Doan, Theresa T (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S612000, C438S614000, C257S700000, C257S758000
Reexamination Certificate
active
07816177
ABSTRACT:
In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.
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Cover page of Japanese Office Action dated Feb. 12, 2008.
Takayanagi Hidenori
Takeuchi Yukiharu
Doan Theresa T
Kratz Quintos & Hanson, LLP
Shinko Electric Industries Co. Ltd.
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