Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

Reexamination Certificate

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C438S199000

Reexamination Certificate

active

07619239

ABSTRACT:
A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

REFERENCES:
patent: 6339232 (2002-01-01), Takagi
patent: 6727550 (2004-04-01), Tezuka et al.
patent: 7115945 (2006-10-01), Lee et al.
patent: 7138309 (2006-11-01), Lee et al.
patent: 7160769 (2007-01-01), White et al.
patent: 7227205 (2007-06-01), Bryant et al.
patent: 2005/0104131 (2005-05-01), Chidambarrao et al.
patent: 2005/0156268 (2005-07-01), Chu
patent: 2001-160594 (2001-06-01), None
patent: 2003-179157 (2003-06-01), None
patent: 2003-203989 (2003-07-01), None
Tsutomu Tezuka et al, “A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs”, 2001, Jpn. J. Apply. Phys., vol. 40, pp. 2866-2874.
T. Irisawa et al, “High current drive uniaxially strained SGOI pmosfets fabricated by lateral strain relaxation technique”, Jun. 14-16, 2005, Symposium on VLSI Technology Digest of Technical Papers, pp. 178-179.
Chinese Patent Office Notification of the First Office Action issued in copending Application No. 2006-10087750.2 mailed Feb. 15, 2008, and English language translation thereof.
Tezuka et al., “Dislocation-free relaxed SiGe-on-insulator mesa structures fabricated by high-temperature oxidation,” Journal of Applied Physics (Dec. 15, 2003), 94:7553-59.
Tezuka et al., “A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs,” Jpn. J. Appl. Phys. (Apr. 2001), 40:2866-74.
Notification for Reasons for Rejection mailed on Jul. 29, 2008, by the Japanese Patent Office in copending Application No. 2005-160525 and English language translation thereof.

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