Static information storage and retrieval – Floating gate – Particular biasing
Patent
1992-12-11
1994-01-11
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
257335, 257345, H01L 2122
Patent
active
052787877
ABSTRACT:
An improved structure of and a method of manufacturing a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a gate region formed on one surface of the substrate and including a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode laminated in that order, source and drain diffusion layers formed on the one surface of the substrate with the gate region disposed between the source and drain diffusion layers, the source and drain diffusion layers having a second conductivity type different from the first conductivity type, and a diffusion layer of the first conductivity type formed in a selected region of the substrate including at least a part of an intermediate region disposed between the source and drain diffusion layers, the diffusion layer of the first conductivity type having an inclined impurity concentration higher than that of the substrate such that the concentration gradually decreases in the direction from the drain diffusion layer toward the source diffusion layer.
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patent: 4949140 (1990-08-01), Tam
patent: 4979005 (1990-12-01), Mitchell
Yoshikawa et al "16M EPROM cell technique" Nikkei Microdevices Jan. 1990 pp. 94-100.
Umezawa et al "A 5V-Only 0.6 Flash EEPROM with Row Decoder Scheme in Triple-Well Structure" SDM 92-2 pp. 7-11.
LaRoche Eugene R.
Le Vu A.
Nippon Steel Corporation
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