Fishing – trapping – and vermin destroying
Patent
1996-06-21
1997-12-09
Niebling, John
Fishing, trapping, and vermin destroying
437 41, 437 57, H01L 21265, H01L 2170
Patent
active
056960085
ABSTRACT:
On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET. A first gate electrode is formed on a side surface of the left second p-type silicon semiconductor layer with a gate insulating film therebetween, and a second gate electrode is formed on a side surface of the right third n-type silicon semiconductor layer with a gate insulating film therebetween.
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Nakaoka Hiroaki
Sugiyama Tatsuo
Tamaki Tokuhiko
Lebentritt Michael S.
Matsushita Electric - Industrial Co., Ltd.
Niebling John
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