Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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C257S277000

Reexamination Certificate

active

11002142

ABSTRACT:
Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer3to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.

REFERENCES:
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patent: 6627512 (2003-09-01), Iwamatsu et al.
patent: 6635550 (2003-10-01), Houston
patent: 6833602 (2004-12-01), Mehta
patent: 2002/0110989 (2002-08-01), Yamaguchi et al.
patent: 9-289324 (1997-11-01), None
patent: 2002-110908 (2002-04-01), None
Yuuichi Hirano, et al., “Impact of 0.10 μm SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Break Trough the Scaling Crisis of Silicon Technology”, IEDM, 2000, pp. 1-4.
Toshiaki Iwamatsu, et al., “Low-Noise and High-Frequency 0.10 μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Netwok LSI”, SSDM, 2003, pp. 1-2.

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