Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor

Reexamination Certificate

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Details

C257S552000, C257S553000, C257S556000, C257S557000, C257S560000, C438S235000, C438S236000

Reexamination Certificate

active

11316908

ABSTRACT:
This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

REFERENCES:
patent: 4746626 (1988-05-01), Eda et al.
patent: 6455364 (2002-09-01), Asai et al.
patent: 6593604 (2003-07-01), Ishimaru
N. Matine et al., “Novel Approach for InP-Based Ultrafast HBTs,”IPRM: Proceedings of Eighth International Conference on Indium Phosphide and Related Materials, 1996, pp. 137-140.

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