Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-05-22
2007-05-22
Doan, Theresa T. (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S118000
Reexamination Certificate
active
11349219
ABSTRACT:
A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.
REFERENCES:
patent: 5477611 (1995-12-01), Sweis et al.
patent: 7157308 (2007-01-01), Takano
patent: 2006/0270106 (2006-11-01), Chiu et al.
patent: 2003-051513 (2003-02-01), None
patent: 2004-500720 (2004-01-01), None
Arai Katsuo
Kagii Hidemasa
Muto Akira
Nakajo Takuya
Nakamura Hiroyuki
Doan Theresa T.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
Renesas Technology Corp.
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