Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S762000, C257S765000, C257S774000

Reexamination Certificate

active

07064441

ABSTRACT:
The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insulation film, a growth suppression film having an opening whose width is wider than that of the Al wiring is formed on the interlayer insulation film and the Al wiring. In this condition, Al and the like are grown by a selective CVD method and the like. Accordingly, the connection pillar is formed on the Al wiring within the opening, in a self-matching manner with respect to the Al wiring.

REFERENCES:
patent: 5783485 (1998-07-01), Ong et al.
patent: 6063703 (2000-05-01), Shinriki et al.
patent: 6215189 (2001-04-01), Toyoda et al.
patent: 6876079 (2005-04-01), Aoyama
patent: 2002/0068427 (2002-06-01), Guo et al.
patent: 08-213391 (1996-08-01), None
patent: 08-339973 (1996-12-01), None

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