Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Patent
1998-02-23
1999-03-30
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
438401, 438462, 438975, H01L 23544, H01L 2176, H01L 21762, H01L 21383
Patent
active
058893350
ABSTRACT:
The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.
REFERENCES:
patent: 4717687 (1988-01-01), Verma
patent: 4737468 (1988-04-01), Martin
patent: 4992394 (1991-02-01), Kostelak et al.
patent: 5369050 (1994-11-01), Kawai
patent: 5578519 (1996-11-01), Cho
Horita Katsuyuki
Kuroi Takashi
Sakai Maiko
Sayama Hirokazu
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Cuong Q.
Thomas Tom
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