Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2005-04-05
2005-04-05
Zarneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S127000
Reexamination Certificate
active
06875639
ABSTRACT:
A semiconductor chip has a quadrangle main surface, a wiring substrate, and a resin seal member for sealing the semiconductor chip, in which the resin seal member has a quadrangle main surface which confronts the main surface of the semiconductor chip. A gate cut trace portion is formed on a side face extending along a first side of the main surface of the resin seal member. A sectional area of an area between the main surface of the wiring substrate and the main surface of the resin seal member at a position outside a side face of the semiconductor chip is smaller than a sectional area of an area between the main surface of the semiconductor chip and the main surface of the resin seal member.
REFERENCES:
patent: 10-135258 (1998-05-01), None
patent: 11-354558 (1999-12-01), None
Arai Hiroshi
Kasai Norihiko
Nagashima Nobuaki
Seki Isao
Hitachi Hokkai Semiconductor Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
Renesas Technology Corp.
Zarneke David A.
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