Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2003-01-29
2004-06-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S244000, C438S253000, C438S387000, C438S396000, C257S068000, C257S071000, C257S295000, C257S296000, C257S306000
Reexamination Certificate
active
06746878
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-072199, filed on Mar. 15, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having capacitors over a semiconductor substrate and a method of manufacturing the same.
2. Description of the Prior Art
In recent years, the semiconductor memory using the ferroelectric capacitor and the high-dielectric capacitor is regarded as the promising one. For example, the ferroelectric capacitor is formed by the steps described in the following.
First, as shown in
FIG. 1A
, the first metal layer
106
, the PZT layer
107
, and the second metal layer
108
are formed sequentially on the interlayer insulating film
104
for covering the semiconductor substrate
101
. In this case, the impurity diffusion region
103
surrounded by the element isolation insulating film
102
is formed on the semiconductor substrate
101
, and the conductive plug
105
is formed in the interlayer insulating film
104
on the impurity diffusion region
103
.
Then, the titanium nitride layer
110
and the silicon oxide layer
111
are formed sequentially on the second metal layer
108
. Then, the silicon oxide layer
111
and the titanium nitride layer
110
are patterned by the photolithography method to be left over the conductive plug
105
as the hard mask
112
having the capacitor planar shape.
Then, as shown in
FIG. 1B
, the second metal layer
108
, the PZT layer
107
, and the first metal layer
106
in the region, which is not covered with the hard mask
112
, are etched sequentially. Thus, the stacked ferroelectric capacitor
113
is formed on the interlayer insulating film
104
.
Then, as shown in
FIG. 1C
, the silicon oxide layer
111
constituting the hard mask
112
is removed, and then the titanium nitride layer
110
is removed by changing the etchant.
As described above, the reason why not the resist mask but the hard mask
112
is employed to pattern the first metal layer
106
, the PZT layer
107
, and the second metal layer
108
is given as follows.
That is, in order to form the stacked ferroelectric capacitor
113
, if the first metal layer
106
, the PZT layer
107
, and the second metal layer
108
are etched successively by using the resist mask, such resist mask disappears during the etching since the resist mask has the poor etching selectivity against these layers
106
,
107
,
108
.
Meanwhile, it is set forth in U.S. Pat. No. 6,169,009 (Patent Application Publication (KOKAI) Hei 11-354510) that the hard mask having the above double-layered structure is used to pattern the metal film and the mixed gas consisting of chlorine, oxygen, and argon is used as the etching gas. Also, it is set forth in Patent Application Publication (KOKAI) Hei 11-354510 that the SiO
2
film in the hard mask disappears in the middle of the etching of the metal film.
It is preferable that the silicon oxide layer should be employed as the hard mask in patterning the PZT layer that is put between the first and second metal layers. Thus, the disappearance of the silicon oxide layer serving as the hard mask during the etching of the PZT layer causes the remarkable reduction in the etching rate of the PZT layer. Therefore, it is important to leave the silicon oxide layer
111
as the hard mask until the etching of the PZT layer is ended.
Accordingly, as shown in
FIG. 1B
, not only the titanium nitride layer
110
constituting the hard mask
112
but also the silicon oxide layer
111
is left on the second metal layer
108
in the state after the etching of the second metal layer
108
, the PZT layer
107
, and the first metal layer
106
are ended.
The silicon oxide layer
111
and the titanium nitride layer
110
are removed by the etching after the formation of the capacitor
113
is completed.
However, when the SiO
2
layer
111
constituting the hard mask
112
is removed, the interlayer insulating film
104
formed of the silicon oxide is also etched around the capacitor
113
. Thus, the level difference between the capacitor
113
and the periphery area is increased. If such level difference is increased, such a disadvantage is caused that the filling property of the second-layer interlayer insulating film between plural capacitors
112
becomes worse.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of making difficult the generation of reduction in thickness of an underlying insulating film when a hard mask used to form a capacitor is removed, and a method of manufacturing the same.
According to one aspect of the present invention, there is provided a semiconductor device comprising: an insulating film formed over a semiconductor substrate; capacitor lower electrodes formed on the insulating film and having discontinuous steps on side surfaces; capacitor dielectric films formed on the capacitor lower electrodes and having side surfaces that continue to upper side surfaces of capacitors; and capacitor upper electrodes formed on the capacitor dielectric films and having side surfaces that continue to side surfaces of the capacitor dielectric films.
Also, the above subject of the present invention can be overcome by providing a semiconductor device manufacturing method which comprises the steps of forming an insulating film over a semiconductor substrate; forming sequentially a first conductive film, a dielectric film, and a second conductive film on the insulating film; forming a first film made of metal or metal compound on the second conductive film; forming a second film made of insulating material on the first film; forming hard masks by patterning the second film and the first film into a capacitor planar shape; forming capacitor upper electrodes by etching the second conductive film in a region that is not covered with the hard masks; forming capacitor dielectric films by etching the dielectric film in the region that is not covered with the hard masks; etching the first conductive film in the region that is not covered with the hard masks up to a depth that does not expose the insulating film; removing the second film constituting the hard masks by etching; forming capacitor lower electrodes by etching a remaining portion of the first conductive film in the region, that is not covered with the hard masks, to the end; and removing the first film constituting the hard masks by the etching.
In addition, the above subject of the present invention can be overcome by providing a semiconductor device manufacturing method which comprises the steps of forming an insulating film over a semiconductor substrate; forming sequentially a first conductive film, a dielectric film, and a second conductive film on the insulating film; forming a first film made of metal or metal compound on the second conductive film; forming a second film made of a silicon nitride film, which is different material from the insulating film, on the first film; forming hard masks by patterning the second film and the first film into a capacitor planar shape; forming capacitor upper electrodes by etching the second conductive film in a region that is not covered with the hard masks; forming capacitor dielectric films by etching the dielectric film in the region that is not covered with the hard masks; forming capacitor lower electrodes by etching the first conductive film in the region that is not covered with the hard masks; removing the second film constituting the hard masks by etching using an etching gas containing fluorine and nitrogen; and removing the first film constituting the hard masks by the etching.
According to the present invention, the insulating material is employed as the uppermost layer of the hard mask that is used to pattern the first conductive film, the dielectric film, and the second conductive film formed on the insulating fil
Komuro Genichi
Suezawa Kenkichi
Fujitsu Limited
Huynh Andy
Nelms David
Westerman Hattori Daniels & Adrian LLP
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