Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-06-11
2004-12-28
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S758000
Reexamination Certificate
active
06835999
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-171371, filed Jun. 12, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device provided with a fuse for a redundancy circuit as seen in a embedded memory device, and in particular, to a semiconductor device which is improved in the fuse and pad portions thereof, and to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
When a fuse for utilizing a redundancy technique is formed on a surface of semiconductor substrate, the fuse is conventionally formed in a metal wiring layer which is disposed next to the second layer as counted downward from the metal pad. However, concomitant with the recent trend to further multiply the wiring layers, the metal wiring layer which is disposed below next to the uppermost metal wiring layer is prone to be made larger in thickness, resulting in an increase in thickness also of the interlayer insulating film which is disposed on the surface of the fuse.
On the occasion of forming a fuse window, it is required not only to work this thickened interlayer insulating film but also to leave the interlayer insulating film on the surface of the fuse. In spite of the requirement that the film thickness of the interlayer insulating film to be left behind on the surface of the fuse be made as thin as possible in order to enable the fuse to be stably cut out by laser blow, the interlayer insulating film to be worked is made very large in thickness, as explained above, thereby making it very difficult to control the working of the interlayer insulating film.
Further, in order to comply with the enhancement of the processing speed of semiconductor devices in recent years, the minimization of the delay of electric current in the metal wiring has become an major problem. It has been considered necessary to employ, as a countermeasure for solving the aforementioned problem, an insulating film which is low in dielectric constant (low-k film) as an interlayer insulating film to be interposed between the metal wirings. In this case, it is quite conceivable to fabricate a structure where this low-k film is disposed next to the second layer as counted downward from the metal pad. If so, the fuse in this low-k film will be cut out by laser blow, which however leads to the damage of this low-k film by the laser blow, thus badly affecting the characteristics and reliability of the semiconductor device.
As explained above, in the case of a semiconductor device such as a embedded memory device, concomitant with the trend to multiply wiring layers, the metal wiring layer which is disposed below next to the uppermost metal wiring layer as well as the interlayer insulating film disposed on the surface of the fuse are prone to be made larger in thickness, and due to this increase in thickness of the interlayer insulating film, it has become very difficult to control the working of the interlayer insulating film on the occasion of forming a fuse window. Further, when a low-k film is employed as an interlayer insulating film in order to enhance the processing speed of semiconductor device, this low-k film will be damaged by the laser blow to be employed in the cutting of the fuse, thus badly affecting the characteristics and reliability of the semiconductor device.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to one embodiment of the present invention comprises:
a semiconductor substrate;
a first metal wiring and a fuse, both being formed as the same level above the semiconductor substrate;
a first insulating film deposited above the semiconductor substrate to cover the first metal wiring and the fuse, the first insulating film having a first pad opening arriving at the first metal wiring;
a second metal wiring formed at least within the first pad opening, the second metal wiring not extending above the fuse;
a stopper film formed on the first insulating film as well as on the second metal wiring; and
a second insulating film formed above the stopper film;
wherein a second pad opening is formed to expose a portion of the second metal wiring by removing the second insulating film and the stopper film, a fuse opening is formed above at least the fuse by removing the second insulating film and the stopper film, and by removing the first insulating film to intermediate in thickness.
A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises:
forming a first metal wiring and a fuse above a semiconductor substrate;
depositing a first insulating film above the semiconductor substrate to cover the first metal wiring and the fuse;
selectively etching the first insulating film deposited on the first metal wiring to form a first pad opening;
selectively forming a second metal wiring to contact with the first metal wiring through the first pad opening;
forming a stopper film on the first insulating film and on the second metal wiring;
forming a second insulating film above the stopper film;
selectively etching parts of the second insulating film which correspond to a portion of the second metal wiring and to at least a portion of the fuse, thereby exposing a part of the stopper film; and
etching away the part of the stopper film that has been exposed by the selective etching of the second insulating film.
REFERENCES:
patent: 4432035 (1984-02-01), Hsieh et al.
patent: 6593207 (2003-07-01), Hong et al.
patent: 2002/0079552 (2002-06-01), Koike
patent: 2004/0012073 (2004-01-01), Omura et al.
patent: 2001-135792 (2001-05-01), None
patent: 2001-176976 (2001-06-01), None
Omura Mitsuhiro
Sato Fumio
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Prenty Mark V.
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