Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1998-07-13
2004-02-17
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S347000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S355000
Reexamination Certificate
active
06693299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device using a crystalline semiconductor thin film, and more particularly to the structure of an insulating gate thin film transistor (TFT). Also, the present invention relates to the structure of a semiconductor circuit, a display unit formed of TFTs, an electro-optic device composing them, and so on.
In the present specification, all of the above TFT, the semiconductor circuit, the electro-optic device and the electronic device belong to semiconductor devices. That is, all of devices which can function using a semiconductor characteristic are called “semiconductor device”. Accordingly, the semiconductor device of the present invention includes not only a single device such as a TFT but also a semiconductor circuit having the single device integrated or an electro-optic device and an electronic device on which such semiconductor circuit and electro-optic device are mounted as components.
2. Description of the Related Art
In recent years, a study relating to a thin film transistor has been advanced at a very high speed. Initially, the thin film transistor had been employed as a pixel switch of the active matrix display unit, but a large amount of study makes the performance of the thin film transistor progressively improve so that the performance of the thin film transistor attains to a stage where an integrated circuit having the performance equal to the conventional IC can be formed at presence.
The existing VLSI and ULSI have a tendency to go on fining the device size to demand further improvement in the integration. The tendency is applied to the TFT, and at presence, there have been demanded such a TFT that its channel length (L) is 1 &mgr;m or less and further 0.2 &mgr;m or less.
On the other hand, there has been known a phenomenon called “short-channel effect” as a factor of preventing the fining in the field of MOSFET. The short-channel effect is directed to various problems such as the deterioration of withstand voltages between a source and a drain of the MOSFET, the deterioration of a threshold value voltage which are induced as the channel length is shortened (refer to Submicron Device I: pp. 88-138, Mitsumasa Koyanagi, et al., Maruzen Kabushiki Kaisha, 1987).
According to this reference book, a punch-through phenomenon has been most well known as one of factors of deteriorating the withstand voltage. This phenomenon is a phenomenon that a potential influence of the shortened channel length on a drain side depletion layer comes to a source side, to thereby lower a diffusion potential of the source side (drain induction barrier lowering phenomenon), with the result that it becomes difficult to control carriers by controlling the gate voltage.
This short-channel effect brings the same problem to TFT which should be overcome to conduct fining. Hereinafter, the mechanism of generating the short-channel effect will be described with reference to a schematic diagram of
FIGS. 2A
to
2
C.
In
FIG. 2A
, reference numeral
201
denotes a substrate having an insulating surface;
202
is a source region;
203
is a drain region,
204
is a pair of low-concentration impurity regions (LDD regions), and
205
is a channel forming region. Those regions
202
to
205
are formed of crystalline semiconductor layers. Also, reference numeral
206
denotes a gate insulating film, and
207
is a gate electrode.
What pays attention to the channel forming region
205
in
FIG. 2A
is a schematic diagram shown in FIG.
2
B. In
FIG. 2B
, a shaded portion indicated by reference numeral
208
is a depletion layer that spreads in the channel forming region.
If usual (in the case where the channel length is long), the depletion layer having a uniform depth is formed under a channel formed directly under the gate electrode
207
. However, as the channel length (L) is extremely shortened, the depletion layer extending from the drain side spreads toward the source region so as to be in contact with the depletion layer of the source side (FIG.
2
B).
As a result, the potential barrier in the vicinity of the source is drawn down by the drain voltage so that a current is allowed to freely flow even in a state where the voltage is not applied to the gate. In this case, an energy band between the source and the drain is continuously varied as shown in FIG.
2
C. This is a punch-through phenomenon that leads to the drop of a withstand voltage between the source and the drain.
Also, the representative example of the short-channel effect is the drop of a threshold value voltage. It is presumed that this is also induced by the spread of the depletion layer.
Various countermeasures have been conducted on the above-described short-channel effect, and the most general countermeasure is a channel doping. The channel doping is a technique in which a slight amount of impurity elements such as P (phosphorus) or B (boron) are added to a shallow degree to the entire channel forming region to suppress the short-channel effect (see Japanese Patent Laid-open Publication No. Hei 4-206971, Japanese Patent Laid-open Publication No. Hei 4-286339, etc.).
The channel doping is conducted for the purpose of controlling the threshold value voltage and suppressing the punch-through. However, the channel doping technique has such a defect that a large limit is given to the electric field effect mobility of a TFT (hereinafter, called “mobility”). In other words, the movement of carriers is impeded by the impurity elements intentionally added, to thereby largely lower the carrier mobility.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problem, and therefore an object of the present invention is to provide a semiconductor device having a completely novel structure which can realize high operation performance (high mobility) and high reliability (high withstand voltage characteristic) together and a method of manufacturing the same.
In order to solve the above problem, according to one aspect of the present invention, there is provided a semiconductor device, comprising:
a crystalline semiconductor film on an insulating surface comprising a source region, a drain region, and an active region; and
a gate insulating film and a gate electrode;
wherein said active region includes at least one channel forming region and at least one impurity region shifting an energy band of said crystalline semiconductor thin film; and
wherein a depletion layer is deterred from spreading from said drain region toward said source region by the impurity region locally disposed.
Also, according to another aspect of the present invention, there is provided a semiconductor device, comprising:
a crystalline semiconductor film on an insulating surface comprising a source region, a drain region, and an active region; and
a gate insulating film and a gate electrode;
wherein said active region includes at least one channel forming region and at least one impurity region shifting an energy band of the crystalline semiconductor film; and
wherein a threshold value voltage is controlled by the impurity region locally disposed.
Further, according to still another aspect of the present invention, there is provided a semiconductor device, comprising:
a crystalline semiconductor film on an insulating surface comprising a source region, a drain region, and an active region; and
a gate insulating film and a gate electrode;
wherein said active region includes at least one channel forming region and at least one impurity region shifting an energy band of said crystalline semiconductor film; and
wherein a depletion layer is deterred from spreading from said drain region toward said source region and a threshold value voltage is controlled by the impurity region locally disposed.
The subject matter of the present invention resides in that the impurity region is locally formed in the active region to suppress the depletion layer that spreads from the drain side to the source side by that impurity region. The active region corresponds to
Fukunaga Takeshi
Mitsuki Toru
Miyanaga Akiharu
Ohtani Hisashi
Yamazaki Shunpei
Abraham Fetsum
Fish & Richardson P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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