Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-12-19
2004-08-24
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S112000, C438S113000, C438S118000, C438S126000, C438S127000
Reexamination Certificate
active
06780679
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method of the same, and, more particularly, to a technique effectively applied to a method of increasing the number of pins used in a resin-encapsulated semiconductor device.
A QFN (Quad Flat Non-leaded package) can be taken as an example of a resin package in which a semiconductor die mounted on a lead frame is encapsulated in a plastic package made of a molding resin.
The QFN has a structure in which: respective lead tips of a plurality of leads electrically connected to a semiconductor die via bonding wires are exposed from the rear surface (lower surface) of the peripheral portion of the plastic package to constitute terminals; and the bonding wires are connected to a surface opposite to the surface on which the terminals are exposed, more specifically, connected to the terminal surfaces inside the plastic package, thereby electrically connecting the terminals and the semiconductor die. The QFN is mounted by soldering these terminals to electrodes (footprint) on a wiring board. This structure has an advantage of the fact that the size of a mounting area is reduced in comparison to a QFP (Quad Flat Package) in which leads transversely extend from the side surface of a package (plastic package) to constitute terminals.
The description of the above QFN is found in Japanese Patent Laid-Open No. 2001-189410 and Japanese Patent Publication No. 3072291, etc.
SUMMARY OF THE INVENTION
However, when it is intended to increase the number of terminals (increase of the number of pins) with higher function and performance of an LSI formed on the semiconductor die, the following problems arise in the QFN.
That is, since the bonding wires are connected to a surface opposite to the terminal surfaces exposed on the rear surface of the plastic package as described above, the interval between the terminals is equal to the interval between the bonding-wire connecting positions of the leads. In addition, it is impossible to reduce an area of the terminal too much because a predetermined are is necessary to ensure the reliability of the mounting.
Therefore, when it is intended to increase the number of pins without changing the size of the package, it is impossible to largely increase the number of pins because the number of terminals cannot be increased to such a degree. On the other hand, when it is intended to increase the number of pins by increasing the size of the package, the length between the semiconductor die and the bonding-wire connecting position becomes wider and the length of the bonding wire becomes longer. Therefore, there arises a problem of the short circuit between the adjoining wires in a wire bonding process and a resin molding process, or the like, which results in a decrease in the manufacturing yield.
Moreover, in the case where the semiconductor die is shrunk with an aim to reduce the manufacturing cost, the length between the semiconductor die and the bonding-wire connecting position becomes wider, whereby there arises also a problem of the fact that the connection by the use of the bonding wire cannot be made.
Also, when it is intended to increase the number of pins by increasing the size of the package, the warp of the package is also increased accordingly. Therefore, particularly, a lifetime of the connection between a terminal located in the peripheral portion of the package and the wiring board becomes shortened due to a temperature cycle or the like after mounting the package onto the wiring board.
An object of the present invention is to provide a technique capable of improving the mounting reliability of a QFN.
Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a QFN.
Another object of the present invention is to provide a technique capable of promoting an increase in the number of pins used in a QFN.
The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.
The typical ones of the inventions disclosed in the present application will be briefly described as follows.
A semiconductor device according to the present invention has: a semiconductor die; a die pad on which said semiconductor die is mounted; a plurality of leads arranged around said semiconductor die; a plurality of wires for electrically connecting said semiconductor die and said leads; and a plastic package for encapsulating said semiconductor die, said die pad, said plurality of leads, and said plurality of wires, wherein said plurality of leads are formed so that intervals between lead tips on one side near said semiconductor die are narrower than those between lead tips on the other side opposite to said one side, and each of said plurality of leads is selectively provided with a terminal, which is formed by pressing and bending a part of each of said leads so as to protrude from a rear surface of said plastic package to the outside
A method of manufacturing a semiconductor device according to the present invention includes the steps of:
(a) press-molding a metal sheet to prepare a lead frame, on which a pattern including said die pad and said plurality of leads is repeatedly formed and a terminal is formed on a surface of each of said plurality of leads so as to protrude in a direction perpendicular to said surface;
(b) mounting a semiconductor die, on each of said plurality of die pads formed on said lead frame, and connecting said semiconductor die and respective parts of said leads by wires;
(c) preparing a molding die having an upper die and a lower die, coating a surface of said lower die with a resin film, then mounting said lead frame on said resin film, and thereby contacting said resin film and said terminal formed on a surface of each of said leads;
(d) sandwiching said resin film and said lead frame between said upper die and said lower die to push a tip portion of said terminal into said resin film;
(e) injecting a resin into a gap between said upper die and said lower die to form a plurality of plastic packages, in which said semiconductor die, said die pad, said leads, and said wires are encapsulated and said terminal protrudes to the outside, and then separating said lead frame from said molding die; and
(f) cutting said lead frame to obtain pieces of said plurality of plastic packages.
REFERENCES:
patent: 5157480 (1992-10-01), McShane et al.
patent: 6365980 (2002-04-01), Carter et al.
patent: 6399423 (2002-06-01), Matsuura et al.
patent: 6427976 (2002-08-01), Huang et al.
patent: 6437429 (2002-08-01), Su et al.
patent: 6563209 (2003-05-01), Takahashi
patent: 2000-100843 (2000-04-01), None
patent: 2000-286372 (2000-10-01), None
patent: 3072291 (2000-11-01), None
patent: 2001-024135 (2001-01-01), None
patent: 2001-189410 (2001-07-01), None
Ito Fujio
Suzuki Hiromichi
Antonelli Terry Stout & Kraus LLP
Vu Hung
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3305590