Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
2002-10-17
2004-11-23
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S268000, C438S420000, C257S110000, C257S341000
Reexamination Certificate
active
06821824
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a manufacturing method for the same, and more particularly to an improvement in performance and an increase in the yield of a power semiconductor device.
BACKGROUND ART
An element using a repeating microscopic structure of p-type and n-type layers wherein an electric field relaxation phenomenon called the RESURF (REduced SURface Field) effect is applied in place of the uniform n-type drift layer of a conventional MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) has been proposed in, for example, U.S. Pat. No. 6,040,600. In this element a low ON resistance is obtained in the ON condition due to the n-type drift layer of which the impurity concentration is higher than the concentration of the uniform n drift layer in the conventional structure by approximately one order while in the OFF condition the entire electric field is relaxed due to a three-dimensional multiple RESURF effect of n/p layers. Thereby, a withstand voltage several times as large as the main withstand voltage conventionally obtained by a high concentration single n-type drift layer alone can be implemented and, in principle, an STM (Super Trench power MOS-FET) structure that can obtain a value lower than the Si limitation (Ron, sp=5.93×10
−9
BV
2.5
, wherein specific resistance is proportional to the main withstand voltage to the power of 2.5) wherein the relationship between the main withstand voltage and the specific ON resistance is limited can be obtained.
In an actual element, however, this repeating microscopic structure of p-type and n-type layers cannot be repeated infinitely in an edge portion of the chip and, therefore, there is a problem wherein a drop in the main withstand voltage is great in a “termination” portion of a termination structure where the repetition ends. In the following, a prior art and problem thereof are described from such a point of view.
FIG. 148
is a cross sectional view schematically showing the first configuration of a semiconductor device according to a prior art and shows a configuration that corresponds to a case where a MOS-FET is posited as a concrete active element structure. In reference to
FIG. 148
, an n
−
epitaxial layer
102
is formed on the first main surface side of an n
+
drain region
101
of the MOS-FET. A pn-repeating structure wherein n-type drift regions
103
and p-type impurity regions
104
are repeated in alternation is formed within this n
−
epitaxial layer
102
.
Here, though the vicinity of the center of this element having the pn-repeating structure is omitted for the purpose of simplification of the description, conventionally a combination of several hundreds to several tens of thousands of repeated pairs of n-type drift regions
103
and p-type impurity regions
104
exists in this portion. The n-type impurity concentration of n-type drift region
103
and the p-type impurity concentration of p-type impurity region
104
in each pair are set at substantially the same level.
A p-type body region
105
is formed on the first main surface side of p-type impurity region
104
. This p-type body region
105
is also located on, at least, a portion of n-type drift region
103
on the first main surface side so as to form a main pn junction with n-type drift region
103
. An n
+
source region
106
of a MOS-FET and a p
+
contact region
107
for making a low resistance contact with p-type body region
105
are formed side by side in the first main surface within this p-type body region
105
.
A gate electrode
109
is formed above the first main surface so as to face p-type body region
105
located between n-type drift region
103
and n
+
source region
106
via a gate insulating film
108
. When a positive voltage is applied to this gate electrode
109
, p-type body region
105
, which faces gate electrode
109
, is inverted to an n-type so that a channel region is formed.
A source electrode
110
made of a material including aluminum (Al), for example, is formed on the first main surface so as to be electrically connected to n
+
source region
106
and p
+
contact region
107
.
A drain metal wire
111
is formed on the second main surface so as to contact n
+
drain region
101
.
Here, in the actual element, the source electrode part is electrically connected to n
+
source region
106
and p
+
contact region
107
through a contact hole provided in an interlayer insulating film on the first main surface and via a barrier metal. In the present application, however, this portion is not important and, therefore, the source electrode part is simplified and expressed using solid lines throughout all of the drawings.
In addition, though n
+
drain region
101
is several times to several tens of times thicker than the effective element portion in the actual element, n
+
drain region
101
is expressed as thinner than the effective element portion in the drawings for the purpose of simplification. In addition to the above, scales, ratios of dimensions, and the like, are deformed in order to simplify the expression and, therefore, the respective dimensions in the drawings are not necessarily precise.
A multiple guard ring structure made of p-type impurity regions
115
, for example, is provided as a termination structure of the pn-repeating structure.
In this configuration, n-type drift regions
103
and p-type impurity regions
104
, respectively, have substantially the same impurity concentration in the center portion and edge portions of the pn-repeating structure.
FIG. 149
is a cross sectional view schematically showing the second configuration of the semiconductor device according to the prior art. In reference to
FIG. 149
, an n
−
epitaxial layer
102
has a buried multi-layer epitaxial structure and a p-type impurity region
104
is formed of a plurality of p-type regions
104
a
that are integrated in the depth direction of the semiconductor substrate in this configuration. In this configuration, p-type impurity regions
104
, respectively, have the same impurity concentration in the center portion and edge portions of the pn-repeating structure.
Here, the concentration distribution in the upward and downward directions of each p-type impurity region
104
is an intrinsic structure and this is a concentration distribution due to the manufacturing method, which has no bearing on the concentration gradient in the part in the lateral direction discussed in the present invention. In addition, though in the drawing the concentration gradient in the upward and downward directions is depicted in only two stages for the purpose of simplification, in practice this concentration sequentially changes.
A manufacturing method according to this prior art is characterized in that n
−
epitaxial layer
102
, having a comparatively high concentration to the extent that the concentration thereof is balanced with that of the p-type layers, is used for the purpose of simplifying the process of formation of the buried layers. A heat treatment is carried out after forming p-type buried diffusion layers
104
a
within n
−
epitaxial layer
102
in such a manner and, therefore, p-type impurity region
104
becomes of a form well-known in Japan as “round sweet balls of confectionary on a skewer.”
FIG. 150
is a cross sectional view schematically showing the third configuration of the semiconductor device according to the prior art. In reference to
FIG. 150
, n-type drift regions
103
and p-type impurity regions
104
form pairs and a trench
123
filled in with a filling
124
is arranged between the members of each combined pn pair in this configuration.
FIG. 151
shows the appearance of electrical field concentration in the structure corresponding to this FIG.
150
. The dark portion in this figure indicates a portion of high electrical field concentration and it is seen that an electrical field concentrates on portions (regions shown by arrows) wherein the pn-repe
Minato Tadaharu
Nitta Tetsuya
Chaudhari Chandra
McDermott Will & Emery LLP
Mitsubishi Denki & Kabushiki Kaisha
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