Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2002-11-20
2004-10-26
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C257S787000
Reexamination Certificate
active
06809405
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method of the same. More particularly, the present invention relates to a technique effectively applicable to the increase of the number of pins used in a resin-encapsulated semiconductor device.
BACKGROUND OF THE INVENTION
A QFN (Quad Flat Non-leaded package) can be taken as an example of a resin package in which a semiconductor die mounted on a lead frame is encapsulated in a plastic package made of molding resin.
In the QFN, tip portions of a plurality of leads electrically connected to a semiconductor die via bonding wires are exposed from a rear surface (lower surface) of a peripheral part of a plastic package, by which terminals are formed. Also, bonding wires are connected to the surfaces opposite to the surfaces on which the terminals are exposed, more specifically, connected to the terminal surfaces inside the plastic package, by which the terminals and the semiconductor die are electrically connected to each other. The QFN is mounted on a wiring board by soldering these terminals to electrodes (footprint) on the wiring board. This structure of the QFN enables to obtain the advantage that the size of the mounting area can be reduced in comparison to a QFP (Quad Flat Package) in which the leads transversely extending from the side surfaces of a package (plastic package) constitute the terminals.
The descriptions of the QFN can be found in Japanese Patent Laid-Open No. 2001-189410 (corresponding U.S. Pat. No. 6,399,423) and Japanese Patent No. 3072291.
SUMMARY OF THE INVENTION
However, when the number of terminals is increased (increase of the number of pins) in accordance with the increasing advancement and higher performance of an LSI formed on the semiconductor die, the following problems arise in the QFN.
That is, since the bonding wires are connected to the surfaces opposite to terminal surfaces exposed on the rear surface of the plastic package as described above, the interval between the terminals is equal to the interval between the tip portions of the leads at which the bonding wires are connected. In addition, since a predetermined size of the terminal is necessary to ensure the reliability of the mounting, it is impossible to reduce the size too much.
Therefore, when it is intended to increase the number of pins without changing the size of the package, it is impossible to largely increase the number of terminals. Thus, it is impossible to largely increase the number of pins. Meanwhile, in the case where the size of the package is increased in order to increase the number of pins, the length between the semiconductor die and the position at which the bonding wire is connected becomes wider, and thus, the length of the bonding wire becomes longer. Therefore, the problem arises, that is, the adjoining wires are short-circuited in the wire bonding process and the resin molding process. As a result, the manufacturing yield is lowered.
Moreover, in the case where the semiconductor die is shrunk with an aim to reduce the manufacturing cost, the length between the semiconductor die and the position at which the bonding wire is connected becomes wider. As a result, the problem is caused, that is, the connection by the use of the bonding wire cannot be made.
An object of the present invention is to provide a technique capable of achieving the increase of the number of pins in a QFN.
Another object of the present invention is to provide a technique to obtain a QFN which is adapted to deal with a die shrink.
The above and other objects and novel characteristics of the present invention will be apparent from the description and the accompanying drawings of this specification.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
A semiconductor device according to the present invention is provided with: a semiconductor die; a die pad on which the semiconductor die is mounted; a plurality of leads arranged around the semiconductor die; a plurality of wires for electrically connecting the semiconductor die and the leads; and a plastic package for encapsulating the semiconductor die, the die pad, the plurality of leads, and the plurality of wires, wherein the plurality of leads are formed so that intervals between lead pits on one side near the semiconductor die are narrower than those between leads tips on the other side opposite to the one side, and a terminal protruded from a rear surface of the plastic package to the outside is selectively provided to each of the plurality of leads.
A method of manufacturing a semiconductor device according to the present invention includes the steps of:
(a) preparing a lead frame on which patterns including the die pad and the plurality of leads are successively formed, and a terminal protruded in a direction perpendicular to a surface of the lead is formed on each surface of the plurality of leads;
(b) mounting a semiconductor die on each of the plurality of die pads formed on the lead frame, and connecting the semiconductor die and the parts of the leads by the use of wires;
(c) preparing a molding die having an upper die and a lower die, coating a surface of the lower die with a resin film, and then, mounting the lead frame on the resin film, thereby bringing the terminal formed on the surface of the lead into contact with the resin film;
(d) pressing the resin film and the lead frame with the upper die and the lower die to push tip portions of the terminals into the resin film;
(e) injecting resin into spaces between the upper and lower dies, thereby encapsulating the semiconductor die, the die pad, the leads, and the wires, and separating the lead frame from the molding die after forming a plurality of plastic packages in which the tip portions of the terminals are protruded to the outside; and
(f) dicing the lead frame to obtain pieces of plastic packages.
REFERENCES:
patent: 08-139259 (1996-05-01), None
patent: 2000-100843 (2000-04-01), None
patent: 2000-3072291 (2000-05-01), None
patent: 2000-286372 (2000-10-01), None
patent: 2001-24135 (2001-01-01), None
patent: 2001-189410 (2001-07-01), None
Ito Fujio
Suzuki Hiromicti
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